Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57501?usp=email )
Change subject: lynxpoint/broadwell: Correct L1 exit latency with ASPM ......................................................................
lynxpoint/broadwell: Correct L1 exit latency with ASPM
Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does the same. Correct the condition accordingly. On Lynx Point, also remove a now-redundant write to the LCAP register (offset 0x4c).
Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501 Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/broadwell/pch/pcie.c M src/southbridge/intel/lynxpoint/pcie.c 2 files changed, 2 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 966a25d..4847da6 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -522,7 +522,7 @@ pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
/* Set L1 exit latency in LCAP register. */ - if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) + if ((pci_read_config8(dev, 0xf5) & 0x1) || do_aspm) pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 0c17c9c..fd41ce8 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -570,9 +570,6 @@ /* Set unique clock exit latency in MPC register. */ pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
- /* Set L1 exit latency in LCAP register. */ - pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); - if (is_lp) { switch (rp) { case 1: @@ -650,7 +647,7 @@ pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
/* Set L1 exit latency in LCAP register. */ - if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) + if ((pci_read_config8(dev, 0xf5) & 0x1) || do_aspm) pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15));