Change in coreboot[master]: soc/intel/alderlake: Implement PMC feature lock

[Eric Lai (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Lean Sheng Tan, Werner Zeh.
Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63691 )

Change subject: soc/intel/alderlake: Implement PMC feature lock
......................................................................

Patch Set 4:

(1 comment)

File src/soc/intel/alderlake/lockdown.c:

https://review.coreboot.org/c/coreboot/+/63691/comment/1aeca627_23046b22 
PS4, Line 28: 		setbits32(pmc_mmio_regs() + PM_CFG, PM_CFG_DBG_MODE_LOCK |
> > Will add more settings? Maybe create a structure to maintain it? If just 3, it's fine. […]

Yes, this is what I mean. And we can use #ifdef CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM) in structure, to make it optimize in built time. I don't expect it will be a lot need to skip.