Attention is currently required from: Haribalaraman Ramasubramanian, Rizwan Qureshi, Meera Ravindranath, Divagar Mohandass.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68251 )
Change subject: soc/intel/alderlake: Add/Remove LTR disqualification ......................................................................
Patch Set 1:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68251/comment/a5da70bf_e7460a61 PS1, Line 7: Add/Remove LTR disqualification for UFS?
https://review.coreboot.org/c/coreboot/+/68251/comment/a63b45f6_d919f9b5 PS1, Line 8: : a) Add LTR disqualification in D3 to ensure PMC ignores LTR : from UFS IP as it is infinite. : b) Remove LTR disqualification in _PS0 to ensure PMC stops : ignoring LTR from UFS IP during D3 exit. reading this recommendation reminds me about some W/A or bug fixes due to UFS sku?
if yes, can I get the doc details ?
Do you have any BUG and TEST case to explain if this code works in proper ?
File src/soc/intel/alderlake/acpi/ufs.asl:
https://review.coreboot.org/c/coreboot/+/68251/comment/504391ca_f6550d59 PS1, Line 73: 0xFE000000 include iomap.h above and replace hardcoded value with `PCH_PWRM_BASE_ADDRESS`
https://review.coreboot.org/c/coreboot/+/68251/comment/850b57e2_99d344df PS1, Line 73: 0x1E30 offset 0x1e30 is not available in external EDS
https://review.coreboot.org/c/coreboot/+/68251/comment/80be64d5_ba15afad PS1, Line 78: // Bit 18, IGN_UFSX2 use /* */
Also, can you please add line to explain what is Bit 18 refers to ?
https://review.coreboot.org/c/coreboot/+/68251/comment/fc2da6f5_5b97b8f8 PS1, Line 91: 0 can u please use a macro `TRUE` and `FALSE` to represent the `0` and `1` then pass those macros accordingly.
ULTR method name is also not clear. may be need one liner to explain
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Subrata Banik (Code Review)