[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81374?usp=email )

(

23 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt
......................................................................

soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt

Domain device objects are created with HID/CID/UID/_OSC/_PXM

Dynamic domain SSDT generation could benefit the support of SoCs with
multiple SKUs, or the case where one set of codes supports multiple
SoCs. One possible side-effect might be the extra performance cost for
generating these tables, which should not bring big impact on high
performance server CPUs.

GNR codes run with dynamic domain SSDT generation to fit for both
GraniteRapids and SierraForest SoCs.

TEST=Build on intel/avenuecity CRB
TEST=Build on intel/beechnutcity CRB

Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c
Signed-off-by: Shuo Liu 
Signed-off-by: Jincheng Li 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81374
Tested-by: build bot (Jenkins) 
Reviewed-by: Lean Sheng Tan 
---
M src/mainboard/intel/avenuecity_crb/dsdt.asl
M src/mainboard/intel/beechnutcity_crb/dsdt.asl
M src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/acpi/uncore.asl
M src/soc/intel/xeon_sp/gnr/soc_acpi.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
6 files changed, 72 insertions(+), 1 deletion(-)

Approvals:
  Lean Sheng Tan: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/intel/avenuecity_crb/dsdt.asl b/src/mainboard/intel/avenuecity_crb/dsdt.asl
index 34c2937..8f84bbe 100644
--- a/src/mainboard/intel/avenuecity_crb/dsdt.asl
+++ b/src/mainboard/intel/avenuecity_crb/dsdt.asl
@@ -13,6 +13,7 @@
 {
    #include <acpi/dsdt_top.asl>
    #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <soc/intel/xeon_sp/gnr/acpi/uncore.asl>
    #include <soc/intel/xeon_sp/gnr/acpi/gpe.asl>
    #include <southbridge/intel/common/acpi/sleepstates.asl>
    #include <commonlib/include/commonlib/console/post_codes.h>
diff --git a/src/mainboard/intel/beechnutcity_crb/dsdt.asl b/src/mainboard/intel/beechnutcity_crb/dsdt.asl
index 34c2937..8f84bbe 100644
--- a/src/mainboard/intel/beechnutcity_crb/dsdt.asl
+++ b/src/mainboard/intel/beechnutcity_crb/dsdt.asl
@@ -13,6 +13,7 @@
 {
    #include <acpi/dsdt_top.asl>
    #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <soc/intel/xeon_sp/gnr/acpi/uncore.asl>
    #include <soc/intel/xeon_sp/gnr/acpi/gpe.asl>
    #include <southbridge/intel/common/acpi/sleepstates.asl>
    #include <commonlib/include/commonlib/console/post_codes.h>
diff --git a/src/soc/intel/xeon_sp/chip_gen6.c b/src/soc/intel/xeon_sp/chip_gen6.c
index 8bbfbe8..686b3e4 100644
--- a/src/soc/intel/xeon_sp/chip_gen6.c
+++ b/src/soc/intel/xeon_sp/chip_gen6.c
@@ -61,6 +61,12 @@
    		pr->Mmio64Base, pr->Mmio64Limit + 1);
 }

+static void iio_pci_domain_fill_ssdt(const struct device *domain)
+{
+	soc_pci_domain_fill_ssdt(domain);
+	pci_domain_fill_ssdt(domain);
+}
+
 static struct device_operations iio_pcie_domain_ops = {
    .read_resources = iio_pci_domain_read_resources,
    .set_resources = pci_domain_set_resources,
@@ -68,7 +74,7 @@
 #if CONFIG(HAVE_ACPI_TABLES)
    .acpi_name = soc_acpi_name,
    .write_acpi_tables = northbridge_write_acpi_tables,
-	.acpi_fill_ssdt	= pci_domain_fill_ssdt,
+	.acpi_fill_ssdt	= iio_pci_domain_fill_ssdt,
 #endif
 };

diff --git a/src/soc/intel/xeon_sp/gnr/acpi/uncore.asl b/src/soc/intel/xeon_sp/gnr/acpi/uncore.asl
new file mode 100644
index 0000000..bc28d62
--- /dev/null
+++ b/src/soc/intel/xeon_sp/gnr/acpi/uncore.asl
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/intel/xeon_sp/acpi/iiostack.asl>
+
+/* TODO: Add other uncore specific ASL files based on needs */
diff --git a/src/soc/intel/xeon_sp/gnr/soc_acpi.c b/src/soc/intel/xeon_sp/gnr/soc_acpi.c
index 6f1df7c..c91ed16 100644
--- a/src/soc/intel/xeon_sp/gnr/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/gnr/soc_acpi.c
@@ -1,10 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <acpi/acpigen.h>
+#include <acpi/acpigen_pci.h>
 #include <assert.h>
 #include <intelblocks/acpi.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/itss.h>
 #include <soc/acpi.h>
+#include <soc/chip_common.h>
+#include <soc/numa.h>
 #include <soc/soc_util.h>
 #include <soc/util.h>
 #include <soc/itss.h>
@@ -39,3 +43,55 @@
 {
    generate_p_state_entries(core, cores_per_package);
 }
+
+static uint32_t get_granted_pcie_features(void)
+{
+	return PCIE_NATIVE_HOTPLUG_CONTROL | PCIE_PME_CONTROL |
+		PCIE_CAP_STRUCTURE_CONTROL | PCIE_LTR_CONTROL |
+		PCIE_AER_CONTROL;
+}
+
+static uint32_t get_granted_cxl_features(void)
+{
+	return CXL_ERROR_REPORTING_CONTROL;
+}
+
+void soc_pci_domain_fill_ssdt(const struct device *domain)
+{
+	const char *name = acpi_device_name(domain);
+	if (!name)
+		return;
+
+	acpigen_write_scope(acpi_device_scope(domain));
+	acpigen_write_device(name);
+
+	if (is_cxl_domain(domain)) {
+		acpigen_write_name("_HID");
+		acpigen_emit_eisaid("ACPI0016");
+		acpigen_write_name("_CID");
+		acpigen_write_package(2);
+		acpigen_emit_eisaid("PNP0A08");
+		acpigen_emit_eisaid("PNP0A03");
+		acpigen_pop_len();
+	} else {
+		acpigen_write_name("_HID");
+		acpigen_emit_eisaid("PNP0A08");
+		acpigen_write_name("_CID");
+		acpigen_emit_eisaid("PNP0A03");
+	}
+	acpigen_write_name("_UID");
+	acpigen_write_string(name);
+
+	acpigen_write_name("_PXM");
+	acpigen_write_integer(device_to_pd(domain));
+
+	/* _OSC */
+	acpigen_write_OSC_pci_domain_fixed_caps(domain,
+		get_granted_pcie_features(),
+		is_cxl_domain(domain),
+		get_granted_cxl_features()
+		);
+
+	acpigen_pop_len();
+	acpigen_pop_len();
+}
diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h
index 3f4c77e..c5553c0 100644
--- a/src/soc/intel/xeon_sp/include/soc/chip_common.h
+++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h
@@ -92,4 +92,6 @@

size_t vtd_probe_bar_size(struct device *dev);

+void soc_pci_domain_fill_ssdt(const struct device *domain);
+
 #endif /* _CHIP_COMMON_H_ */