[XS] Change in coreboot[main]: mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support

[Jian Tong (Code Review)]

Attention is currently required from: Karthik Ramasubramanian, Paul Menzel, Subrata Banik.

Hello Karthik Ramasubramanian, Kun Liu, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/84177?usp=email

to look at the new patch set (#6).

Change subject: mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support
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mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support

Power consumption according to RTS5227 datasheet section 6.4, L0s is not supported, so set it to ASPM_L1.

lspci -vvvv -s 01:00 to verify LnkCtl: ASPM L1 Enabled.

BUG=b:359409425
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage

Change-Id: I87bb0d195566d273951dee6eeb54c9b388dd7607
Signed-off-by: Jian Tong 
---
M src/mainboard/google/brox/variants/lotso/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/84177/6