Change in coreboot[master]: soc/intel/cannonlake: Add ramstage uart debug support

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded a new patch set (#4). ( https://review.coreboot.org/21412 )

Change subject: soc/intel/cannonlake: Add ramstage uart debug support
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soc/intel/cannonlake: Add ramstage uart debug support

Using fixed resources for LPSS uart devices for debugging purpose.

Change-Id: Ib773e01d5f5358f13297400075d6920793200b88
Signed-off-by: Lijian Zhao 
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M src/soc/intel/cannonlake/Makefile.inc
A src/soc/intel/cannonlake/uart_pch.c
2 files changed, 61 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/21412/4