[XS] Change in coreboot[main]: soc/intel/common/block/acpi/exclude DMI fixed memory range if no DMI

[Cliff Huang (Code Review)]

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84349?usp=email )

Change subject: soc/intel/common/block/acpi/exclude DMI fixed memory range if no DMI
......................................................................

soc/intel/common/block/acpi/exclude DMI fixed memory range if no DMI

exclude DMI in northbridge.asl if DMI_BASE_SIZE is '0'

BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
     for PTL using google/fatcat mainboard.

Signed-off-by: Cliff Huang 
Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d
---
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
1 file changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/84349/1

diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
index 51b0e23..1f9c7a4 100644
--- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl
+++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
@@ -291,12 +291,12 @@
    		 * B0:D0:F0:Reg.48h
    		 */
    		Memory32Fixed (ReadWrite, 0, MCH_BASE_SIZE, MCHB)
-
+#if DMI_BASE_SIZE != 0
    		/* DMI BAR _BAS will be updated in _CRS below according to
    		 * B0:D0:F0:Reg.68h
    		 */
    		Memory32Fixed (ReadWrite, 0, DMI_BASE_SIZE, DMIB)
-
+#endif
    		/* EP BAR _BAS will be updated in _CRS below according to
    		 * B0:D0:F0:Reg.40h
    		 */
@@ -322,10 +322,10 @@

CreateDwordField (BUF0, MCHB._BAS, MBR0)
    	MBR0 = _SB.PCI0.GMHB ()
-
+#if DMI_BASE_SIZE != 0
    	CreateDwordField (BUF0, DMIB._BAS, DBR0)
    	DBR0 = _SB.PCI0.GDMB ()
-
+#endif
    	CreateDwordField (BUF0, EGPB._BAS, EBR0)
    	EBR0 = _SB.PCI0.GEPB ()