Change in coreboot[master]: rockchip/rk3399: add the delay time between saradc power up and start...

[Lin Huang (Code Review)]

Lin Huang has uploaded this change for review. ( https://review.coreboot.org/23515

Change subject: rockchip/rk3399: add the delay time between saradc power up and start command
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rockchip/rk3399: add the delay time between saradc power up and start command

We found when ambient temperature low, with now saradc frequency and the
delay time between saradc power up and start command, there may get wrong
adc value, then get the wrong ramid or boardid, so lower the saradc frequency
and add the delay time between power up and start command.

Change-Id: I42e49ca63299479912fa05e2a62cba6f2de4b337
Signed-off-by: Lin Huang 
---
M src/soc/rockchip/rk3399/saradc.c
1 file changed, 3 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/23515/1

diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c
index d70c966..a068b80 100644
--- a/src/soc/rockchip/rk3399/saradc.c
+++ b/src/soc/rockchip/rk3399/saradc.c
@@ -46,20 +46,12 @@
 /* SARADC_DATA, 10[0:9] bits */
 #define DATA_MASK		0x3FF

-/* The max clk is 13 MHz, we also recommended that
- * the sample rate(=clk/13) should be > 500KHz.
- * So choose 8MHz, that 8MHz/13 = 615.38KHz > 500KHz.
- */
-#define SARADC_HZ		(8*MHz)
-
-/* TRM(V0.3 Part 1 Page 366) said there is a delay between
- * power up and start command, default value is 2 src clk.
- * Let delay 2 src clk here, in ns(udelay).
- */
-#define SARADC_DELAY_PU		(1 * 1000 * 1000 * 1000 / SARADC_HZ * 2)
+#define SARADC_HZ		(1*MHz)

#define SARADC_MAX_CHANNEL	6

+#define SARADC_DELAY_PU                (1 * 1000 * 1000 * 1000 / SARADC_HZ * 8)
+
 u32 get_saradc_value(u32 chn)
 {
    u32 adc_value;