[S] Change in coreboot[master]: soc/intel/apollolake: Fix FSP SATA speed limit configuraion

[Werner Zeh (Code Review)]

Attention is currently required from: Eric Lai, Felix Singer, Jan Samek, Mario Scheithauer, Sean Rhodes.

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75820?usp=email )

Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
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Patch Set 8: Code-Review+1

(2 comments)

Patchset:

PS7:
> Oh wow. […]

There can be hardware related topics on the PCB (layout, signal quality, ...) which can enforce one to step back to a lower speed grade than the maximum supported by both endpoints to guarantee a proper operation of the link in all circumstances.
Since in some applications (which our case belongs to) the real data throughput an SSD device can provide is much more lower that the theoretical throughput of the SATA interface, there is no real point in having the higher speed grade enabled because it in the end will not provide a higher bandwidth. And in this cases it is better to get a reliable link by reducing the SATA speed grade.

File src/soc/intel/apollolake/ahci.c:

https://review.coreboot.org/c/coreboot/+/75820/comment/d3db37ac_779d4447 :
PS7, Line 12: 	if (speed == SATA_DEFAULT)
            :
> Done

This was added in order to keep the interference with existing code as low as possible. When a mainboard does not provide the parameter in the devicetree nothing is changed and the behavior stays as it was.