Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43916 )
Change subject: mb/intel/saddlebrook: Relocate devicetree FSP settings ......................................................................
mb/intel/saddlebrook: Relocate devicetree FSP settings
Some settings are suspicious, and have been annotated with FIXMEs.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: Ib6cf9bcc45042641054fbdca85f69b50292f706b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/saddlebrook/devicetree.cb 1 file changed, 71 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43916/1
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index d3ca269..3365b05 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -18,16 +18,9 @@ register "speed_shift_enable" = "1"
# FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "0" - register "Heci3Enabled" = "0"
register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" @@ -118,30 +111,6 @@ .voltage_limit = 1520, }"
- # Enable x1 slot - register "PcieRpEnable[7]" = "1" - register "PcieRpClkReqSupport[7]" = "1" - register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 - - # Enable x4 slot - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - - # Enable Root port 6 and 13. - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[12]" = "1" - - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqSupport[12]" = "1" - - # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[5]" = "0" - register "PcieRpClkReqNumber[12]" = "1" - - register "EnableLan" = "1" - # USB related register "SsicPortEnable" = "1"
@@ -171,22 +140,7 @@ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
- register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - # Must leave UART0 enabled or SD/eMMC will not work as PCI - - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 1, \ - [5] = 1, \ - [6] = 1, \ - [7] = 1, \ - }" register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoPci, \ [PchSerialIoIndexI2C1] = PchSerialIoPci, \ @@ -209,15 +163,16 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- # Use default SD card detect GPIO configuration - #register "sdcard_cd_gpio_default" = "GPP_A7" - device cpu_cluster 0 on device lapic 0 on end end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + + # Disable SA thermal device + register "Device4Enable" = "0" + device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem @@ -229,37 +184,90 @@ device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA + device pci 16.4 off # Management Engine Interface 3 + register "Heci3Enabled" = "0" + end + device pci 17.0 on # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + end device pci 19.0 on end # UART #2 device pci 19.1 on end # I2C #5 - device pci 19.2 on end # I2C #4 + device pci 19.2 on # I2C #4 + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + end device pci 1c.0 on end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.5 off # PCI Express Port 6 + + # FIXME: Root port is disabled! + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "0" + end device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 + device pci 1c.7 off # PCI Express Port 8 + + # FIXME: Root port is disabled! + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "3" + end + device pci 1d.0 off # PCI Express Port 9 + + # FIXME: Root port is disabled! + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 + + # FIXME: Corresponding device entry missing + register "PcieRpEnable[12]" = "1" + register "PcieRpClkReqSupport[12]" = "1" + register "PcieRpClkReqNumber[12]" = "1" + device pci 1e.0 on end # UART #0 device pci 1e.1 on end # UART #1 device pci 1e.2 on end # GSPI #0 device pci 1e.3 on end # GSPI #1 - device pci 1e.4 off end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard - device pci 1f.0 on - end # LPC Interface + device pci 1e.4 off # eMMC + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + end + device pci 1e.5 off end # SDIO + device pci 1e.6 off # SDCard + register "ScsSdCardEnabled" = "0" + end + device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.3 on # Intel HDA + register "EnableAzalia" = "1" + end + device pci 1f.4 on # SMBus + register "SmbusEnable" = "1" + end device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device pci 1f.6 on # GbE + register "EnableLan" = "1" + end + + register "EnableTraceHub" = "0" end end
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43916
to look at the new patch set (#2).
Change subject: mb/intel/saddlebrook: Relocate devicetree settings ......................................................................
mb/intel/saddlebrook: Relocate devicetree settings
Some settings are suspicious, and have been annotated with FIXMEs.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: Ib6cf9bcc45042641054fbdca85f69b50292f706b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/saddlebrook/devicetree.cb 1 file changed, 71 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43916/2
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43916 )
Change subject: mb/intel/saddlebrook: Relocate devicetree settings ......................................................................
Abandoned
-
Angel Pons (Code Review)