Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim.
Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email )
Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ......................................................................
Patch Set 44:
(1 comment)
File src/soc/intel/pantherlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/83789/comment/87dc7caf_74ed51fe?usp... : PS17, Line 54: .port = PID_GPIOCOM0,
For constructing PCR addresses to access the register, 8-bit port id is used. When accessing from outside of PCD, 16bit is used the first byte is segment ID, followed by 8bit port id. For instance, for IOM to access GPIO registers, segment ID is needed for global routing, who's value is 0xf2. The 2nd set of PID defines is needed for cpu_port:
#define SEGMENTID_CHIPSET0 0xf2 #define PID16_CHIPSET0(x) ((SEGMENTID_CHIPSET0 << 8) | x) #define PID16_GPIOCOM0 PID16_CHIPSET0(PID_GPIOCOM0) #define PID16_GPIOCOM1 PID16_CHIPSET0(PID_GPIOCOM1) #define PID16_GPIOCOM3 PID16_CHIPSET0(PID_GPIOCOM3) #define PID16_GPIOCOM4 PID16_CHIPSET0(PID_GPIOCOM4) #define PID16_GPIOCOM5 PID16_CHIPSET0(PID_GPIOCOM5)
The field has been changed in the typec AUX bias cntrl registers in PTL. The port id is now 16-bit.
15:0 RW 0x0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID 18:16 RW 0x0 BIT_NUM Data bit Position in PCH GPIO 31:24 RW 0x0 VW_INDEX VW Index in PCH GPIO
what you have explained is the SoC internal logic to access IPs across the Die. But here AP FW running as part of Host CPU should be able to access GPIO controllers in the same manner as Port ID 8-bit address. I don't see any need to change that. If IOM FW is accessing GPIO controllers then it needs to create the address with 16-bit PID because of outside of the die access.
Btw, I thought TCSS is also part of PCD die (unlike MTL where we had IOE die) hence, I'm not sure if I follow what you mean by "accessing outside PCD die"? Both GPIO and TCSS are part of the PCD die isn't it ?
looks like you are saying, the cpu_port will use some internal logic now while programming the GPIO controller hence, we need to support 16-bit cpu_port. If that is the case, then please follow my advice of adding a Kconfig which is true for PTL and then
can you please help me to understand the register big definition difference between
PTL:
``` 15:0 RW 0x0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID 18:16 RW 0x0 BIT_NUM Data bit Position in PCH GPIO 31:24 RW 0x0 VW_INDEX VW Index in PCH GPIO ```
and previous generations?
wondering if "GROUP_ID Group ID in PCH GPIO" was 8-bit previously ? I don't find this into the EDS.