[XL] Change in coreboot[main]: soc/intel/ptl: Add memory, romstage and ramstage FSP programming

[Jérémy Compostella (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Chen, Kapil Porwal, Pranava Y N, Subrata Banik.

Hello Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Chen, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/84443?usp=email

to look at the new patch set (#6).

Change subject: soc/intel/ptl: Add memory, romstage and ramstage FSP programming
......................................................................

soc/intel/ptl: Add memory, romstage and ramstage FSP programming

BUG=348678529
TEST=Boot to UI on google fatcat board

Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6988
Signed-off-by: Jeremy Compostella 
---
M src/soc/intel/pantherlake/fsp_params.c
M src/soc/intel/pantherlake/include/soc/meminit.h
M src/soc/intel/pantherlake/meminit.c
M src/soc/intel/pantherlake/romstage/fsp_params.c
4 files changed, 1,186 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/84443/6