[M] Change in coreboot[main]: mb/google/brox/var/lotso: Configure cpu power limits by battery status

[Jian Tong (Code Review)]

Jian Tong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84202?usp=email )

Change subject: mb/google/brox/var/lotso: Configure cpu power limits by battery status
......................................................................

mb/google/brox/var/lotso: Configure cpu power limits by battery status

When battery not persent, limit PL4 to 40.

BUG=b:355094551
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage

Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928
Signed-off-by: Jian Tong 
---
M src/mainboard/google/brox/variants/lotso/Makefile.mk
M src/mainboard/google/brox/variants/lotso/overridetree.cb
A src/mainboard/google/brox/variants/lotso/ramstage.c
3 files changed, 79 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/84202/1

diff --git a/src/mainboard/google/brox/variants/lotso/Makefile.mk b/src/mainboard/google/brox/variants/lotso/Makefile.mk
index c88fed9..6c3ef5a 100644
--- a/src/mainboard/google/brox/variants/lotso/Makefile.mk
+++ b/src/mainboard/google/brox/variants/lotso/Makefile.mk
@@ -5,3 +5,4 @@
 romstage-y += gpio.c
 ramstage-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-y += ramstage.c
\ No newline at end of file
diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb
index 85a3506..78d73b3 100644
--- a/src/mainboard/google/brox/variants/lotso/overridetree.cb
+++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb
@@ -74,8 +74,7 @@

register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
    	.tdp_pl1_override = 15,
-		.tdp_pl2_override = 40,
-		.tdp_pl4 = 57,
+		.tdp_pl2_override = 25,
    }"

device domain 0 on
diff --git a/src/mainboard/google/brox/variants/lotso/ramstage.c b/src/mainboard/google/brox/variants/lotso/ramstage.c
new file mode 100644
index 0000000..075ccb9
--- /dev/null
+++ b/src/mainboard/google/brox/variants/lotso/ramstage.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
+
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ * Following values are for performance config as per document #640982
+ */
+
+const struct cpu_power_limits performance_efficient_limits[] = {
+	{
+		.mchid = PCI_DID_INTEL_RPL_P_ID_3,
+		.cpu_tdp = 15,
+		.pl1_min_power = 15000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 25000,
+		.pl2_max_power = 25000,
+		.pl4_power = 114000
+	},
+	{
+		.mchid = PCI_DID_INTEL_RPL_P_ID_4,
+		.cpu_tdp = 15,
+		.pl1_min_power = 15000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 25000,
+		.pl2_max_power = 25000,
+		.pl4_power = 114000
+	},
+};
+
+const struct cpu_power_limits power_optimized_limits[] = {
+	{
+		.mchid = PCI_DID_INTEL_RPL_P_ID_3,
+		.cpu_tdp = 15,
+		.pl1_min_power = 15000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 25000,
+		.pl2_max_power = 25000,
+		.pl4_power = 40000
+	},
+	{
+		.mchid = PCI_DID_INTEL_RPL_P_ID_4,
+		.cpu_tdp = 15,
+		.pl1_min_power = 15000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 25000,
+		.pl2_max_power = 25000,
+		.pl4_power = 40000
+	},
+};
+
+void __weak variant_devtree_update(void)
+{
+
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+
+	const struct cpu_power_limits *limits = performance_efficient_limits;
+	size_t limits_size = ARRAY_SIZE(performance_efficient_limits);
+
+	/*
+	 * If battery is not present or battery level is at or below critical threshold
+	 * to boot a platform with the performance efficient configuration, boot with
+	 * the power optimized configuration.
+	 */
+	if (CONFIG(EC_GOOGLE_CHROMEEC)) {
+		if (!google_chromeec_is_battery_present_and_above_critical_threshold()) {
+			limits = power_optimized_limits;
+			limits_size = ARRAY_SIZE(power_optimized_limits);
+		}
+	}
+
+	variant_update_power_limits(limits, limits_size);
+}