Attention is currently required from: Raul Rangel, Jon Murphy, Paul Menzel, Tim Van Patten, Mark Hasemeyer.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74106 )
Change subject: mb/google/myst: Add ACPI configuration for USB ports ......................................................................
Patch Set 25:
(2 comments)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74106/comment/71706cc1_0650ddf7 PS25, Line 24: chip drivers/usb/acpi : register "desc" = ""USB3 Type-C Port C0 (MLB)"" : register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" : register "group" = "ACPI_PLD_GROUP(1, 1)" : device ref usb3_port0 on end : end : chip drivers/usb/acpi : register "desc" = ""USB3 Type-C Port C1 (MLB)"" : register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" : register "group" = "ACPI_PLD_GROUP(1, 2)" : device ref usb3_port1 on end : end : chip drivers/usb/acpi : register "desc" = ""USB2 Type-C Port C0 (MLB)"" : register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" : register "group" = "ACPI_PLD_GROUP(1, 1)" : device ref usb2_port0 on end : end : chip drivers/usb/acpi : register "desc" = ""USB2 Type-C Port C1 (MLB)"" : register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" : register "group" = "ACPI_PLD_GROUP(1, 2)" : device ref usb2_port1 on end : end These are USB-A0 or USB-A1 ports.
USB-C0 and USB-C1 ports are routed to USB4 capable XHCI controllers which are in gpp_bridge_c. Those ports are USB4/USB3.1g2/USB2 compatible. You have set them up correctly there.
https://review.coreboot.org/c/coreboot/+/74106/comment/bb0207cd_c9052c35 PS25, Line 102: register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" Use custom_pld. Please refer to skyrim or other google mainboards. Same for all user-visible ports.
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Karthik Ramasubramanian (Code Review)