Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE

[Angel Pons (Code Review)]

Attention is currently required from: Arthur Heymans, Nico Huber, Martin Roth, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Lean Sheng Tan, Patrick Rudolph, Felix Held.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )

Change subject: soc/intel/elkhartlake: Introduce Intel PSE
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Patch Set 55:

(1 comment)

File src/soc/intel/elkhartlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/55367/comment/56d90534_090c4c1e 
PS52, Line 129: /* Set the ownership of these devices to PSE */
              : 		params->PchPseDmaEnable[0] = PSE_Owned;
              : 		params->PchPseUartEnable[2] = PSE_Owned;
              : 		params->PchPseHsuartEnable[2] = PSE_Owned;
              : 		params->PchPseI2cEnable[2] = PSE_Owned;
              : 		params->PchPseTimedGpioEnable[0] = PSE_Owned;
              : 		params->PchPseTimedGpioEnable[1] = PSE_Owned;
              : 		/* Disable PSE DMA Sideband Interrupt for DMA 0 */
              : 		params->PchPseDmaSbInterruptEnable[0] = 0;
              : 		/* Set the log output to PSE UART 2 */
              : 		params->PchPseLogOutputChannel = 3;
> Unfortunately for EHL PSE to work we need to enable these params, hence I have to put here so mainbo […]

Without knowing the reasons why these settings are required, I'm afraid I can't think of a better approach.