Patch set updated for coreboot: d2ac8c5 haswell: Link stage_cache_external_region into ramstage, too

[Sol Boucher]

Sol Boucher ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10046

-gerrit

commit d2ac8c57906098fe8e065f01b859d3ad27dcd7f3
Author: Sol Boucher 
Date:   Thu Apr 30 18:02:08 2015 -0700

haswell: Link stage_cache_external_region into ramstage, too

When CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM is set, this
    function is now linked into the ramstage as well as the romstage,
    since the former makes calls to it in panther builds.
    With this commit, it's possible to build panther using the config file
    from the Chromium OS project[1] if you supply the appropriate Intel
    descriptor and ME binary blobs and manually set
    CONFIG_VBOOT_VERIFY_FIRMWARE=n, CONFIG_BUILD_WITH_FAKE_IFD=n, and
    CONFIG_HAVE_ME_BIN=y. The resulting image is at least able to load a
    payload, although I only tested with depthcharge, which immediately
    complained, "vboot handoff pointer is NULL" and gave up the ghost.

[1] https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/m...

Change-Id: Id3bb510fa60129a4d36a0117dc33e7aa62d6c742
    Signed-off-by: Sol Boucher 
---
 src/cpu/intel/haswell/Makefile.inc  |  3 +++
 src/cpu/intel/haswell/romstage.c    | 10 ----------
 src/cpu/intel/haswell/stage_cache.c | 30 ++++++++++++++++++++++++++++++
 3 files changed, 33 insertions(+), 10 deletions(-)

diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index 0db0475..57f9120 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -4,9 +4,12 @@ romstage-y += romstage.c
 romstage-y += tsc_freq.c

ramstage-y += acpi.c
+ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
 ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c

+romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c

smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index b8c455b..8e4335f 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -20,7 +20,6 @@
 #include <stdint.h>
 #include <string.h>
 #include <cbfs.h>
-#include <cbmem.h>
 #include <console/console.h>
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
@@ -313,15 +312,6 @@ void romstage_after_car(void)

#if IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)
-
-void stage_cache_external_region(void **base, size_t *size)
-{
-	/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
-	 * The top of ram is defined to be the TSEG base address. */
-	*size = RESERVED_SMM_SIZE;
-	*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
-}
-
 void ramstage_cache_invalid(void)
 {
 #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c
new file mode 100644
index 0000000..162a244
--- /dev/null
+++ b/src/cpu/intel/haswell/stage_cache.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbmem.h>
+#include <stage_cache.h>
+#include "haswell.h"
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+	/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+	 * The top of ram is defined to be the TSEG base address. */
+	*size = RESERVED_SMM_SIZE;
+	*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
+}