Change in coreboot[master]: soc/intel/skylake: Move UNCORE PRMRR base and mask defines.

[Pratikkumar V Prajapati (Code Review)]

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21247

Change subject: soc/intel/skylake: Move UNCORE PRMRR base and mask defines.
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soc/intel/skylake: Move UNCORE PRMRR base and mask defines.

UNCORE PRMRR BASE and MASK MSRs are not common, so move to
SOC specific header file and rename the #define to start with MSR_*

Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170
Signed-off-by: Pratik Prajapati 
---
M src/soc/intel/common/block/include/intelblocks/msr.h
M src/soc/intel/skylake/include/soc/msr.h
M src/soc/intel/skylake/smmrelocate.c
M src/soc/intel/skylake/systemagent.c
4 files changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/21247/1

diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 55d0bfd..6236915 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -72,8 +72,6 @@
 #define  PRMRR_PHYS_MASK_VALID		(1 << 11)
 #define MSR_POWER_CTL			0x1fc
 #define MSR_EVICT_CTL			0x2e0
-#define UNCORE_PRMRR_PHYS_BASE_MSR	0x2f4
-#define UNCORE_PRMRR_PHYS_MASK_MSR	0x2f5
 #define MSR_SGX_OWNEREPOCH0		0x300
 #define MSR_SGX_OWNEREPOCH1		0x301
 #define IA32_MC0_CTL			0x400
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index 4ff4ad2..0bd7f3c 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -32,6 +32,8 @@
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define IA32_PLATFORM_DCA_CAP		0x1f8
 #define MSR_LT_LOCK_MEMORY		0x2e7
+#define MSR_UNCORE_PRMRR_PHYS_BASE	0x2f4
+#define MSR_UNCORE_PRMRR_PHYS_MASK	0x2f5
 #define MSR_VR_CURRENT_CONFIG		0x601
 #define MSR_VR_MISC_CONFIG		0x603
 #define MSR_VR_MISC_CONFIG2		0x636
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 482107b..dbe0c94 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -50,8 +50,8 @@
           "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n",
           relo_params->uncore_emrr_base.lo,
           relo_params->uncore_emrr_mask.lo);
-	wrmsr(UNCORE_PRMRR_PHYS_BASE_MSR, relo_params->uncore_emrr_base);
-	wrmsr(UNCORE_PRMRR_PHYS_MASK_MSR, relo_params->uncore_emrr_mask);
+	wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base);
+	wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask);
 }

static void update_save_state(int cpu, uintptr_t curr_smbase,
diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c
index c1733df..8e3276d 100644
--- a/src/soc/intel/skylake/systemagent.c
+++ b/src/soc/intel/skylake/systemagent.c
@@ -66,12 +66,12 @@

int soc_get_uncore_prmmr_base(msr_t *prmrr_base)
 {
-	*prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR);
+	*prmrr_base = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE);
    return 1;
 }

int soc_get_uncore_prmmr_mask(msr_t *prmrr_mask)
 {
-	*prmrr_mask = rdmsr(UNCORE_PRMRR_PHYS_MASK_MSR);
+	*prmrr_mask = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK);
    return 1;
 }