Attention is currently required from: Ron Minnich. Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57082 )
Change subject: src/mainboard/emulation/qemu-power9: require hb-mode=on ......................................................................
src/mainboard/emulation/qemu-power9: require hb-mode=on
coreboot must be run the same way it's run on hardware, that is as firmware.
Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Signed-off-by: Yaroslav Kurlaev yaroslav.kurlaev@3mdeb.com --- M src/arch/ppc64/rom_media.c M src/arch/ppc64/stages.c M src/mainboard/emulation/qemu-power9/memlayout.ld 3 files changed, 32 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/57082/1
diff --git a/src/arch/ppc64/rom_media.c b/src/arch/ppc64/rom_media.c index 7d849e4..59b182e 100644 --- a/src/arch/ppc64/rom_media.c +++ b/src/arch/ppc64/rom_media.c @@ -2,10 +2,8 @@
#include <boot_device.h>
-/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(0x8000000, CONFIG_ROM_SIZE);
const struct region_device *boot_device_ro(void) { diff --git a/src/arch/ppc64/stages.c b/src/arch/ppc64/stages.c index 20ed723..01b9efa 100644 --- a/src/arch/ppc64/stages.c +++ b/src/arch/ppc64/stages.c @@ -13,10 +13,23 @@
#include <cbmem.h> #include <arch/stages.h> +#include <cpu/power/spr.h>
void stage_entry(uintptr_t stage_arg) { +#if ENV_RAMSTAGE + uint64_t hrmor; +#endif + if (!ENV_ROMSTAGE_OR_BEFORE) _cbmem_top_ptr = stage_arg; + +#if ENV_RAMSTAGE + hrmor = read_spr(SPR_HRMOR); + asm volatile("sync; isync" ::: "memory"); + write_spr(SPR_HRMOR, 0); + asm volatile("or 1,1,%0; slbia 7; sync; isync" :: "r"(hrmor) : "memory"); +#endif + main(); } diff --git a/src/mainboard/emulation/qemu-power9/memlayout.ld b/src/mainboard/emulation/qemu-power9/memlayout.ld index 42e3889..14f491e 100644 --- a/src/mainboard/emulation/qemu-power9/memlayout.ld +++ b/src/mainboard/emulation/qemu-power9/memlayout.ld @@ -10,14 +10,24 @@
BOOTBLOCK(0, 32K)
- ROMSTAGE(0xf00000, 1M) - STACK(0x1000000, 32K) - RAMSTAGE(0x1008000, 1M) + ROMSTAGE(0x1f00000, 1M) +#if !ENV_RAMSTAGE + STACK(0x2000000, 32K) + RAMSTAGE(0x2008000, 1M)
- FMAP_CACHE(0x1108000, 4K) - CBFS_MCACHE(0x1109000, 8K) - TIMESTAMP(0x110b000, 4K) - CBFS_CACHE(0x110c000, 512K) - PRERAM_CBMEM_CONSOLE(0x118c000, 128K) + FMAP_CACHE(0x2108000, 4K) + CBFS_MCACHE(0x2109000, 8K) + TIMESTAMP(0x210b000, 4K) + CBFS_CACHE(0x210c000, 512K) + PRERAM_CBMEM_CONSOLE(0x218c000, 128K) +#else + STACK(0xa000000, 32K) + RAMSTAGE(0xa008000, 1M)
+ FMAP_CACHE(0xa108000, 4K) + CBFS_MCACHE(0xa109000, 8K) + TIMESTAMP(0xa10b000, 4K) + CBFS_CACHE(0xa10c000, 512K) + PRERAM_CBMEM_CONSOLE(0xf918c000, 128K) +#endif }