Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41868 )
Change subject: [WIP]mb/gigabyte/ga-g41m-combo: Add variant ......................................................................
[WIP]mb/gigabyte/ga-g41m-combo: Add variant
Untested.
Change-Id: I2752b259ff4a0612a7de1c8a3a9a79a3a070cdfc Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/gigabyte/ga-g41m-es2l/Kconfig M src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name A src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/gpio.c A src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/hda_verb.c A src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/overridetree.cb A src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/superio.c 6 files changed, 247 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/41868/1
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 97f155a..5137c96 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only
-if BOARD_GIGABYTE_GA_G41M_ES2L +if BOARD_GIGABYTE_GA_G41M_ES2L || BOARD_GIGABYTE_GA_G41M_COMBO
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -8,12 +8,13 @@ select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_ITE_IT8718F if BOARD_GIGABYTE_GA_G41M_ES2L + select SUPERIO_ITE_IT8720F if BOARD_GIGABYTE_GA_G41M_COMBO select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE - select REALTEK_8168_RESET + select REALTEK_8168_RESET if BOARD_GIGABYTE_GA_G41M_ES2L select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME @@ -27,6 +28,7 @@ config VARIANT_DIR string default "ga-g41m-es2l" if BOARD_GIGABYTE_GA_G41M_ES2L + default "ga-g41m-combo" if BOARD_GIGABYTE_GA_G41M_COMBO
config OVERRIDE_DEVICETREE string @@ -35,9 +37,14 @@ config MAINBOARD_PART_NUMBER string default "GA-G41M-ES2L" if BOARD_GIGABYTE_GA_G41M_ES2L + default "G41M-Combo" if BOARD_GIGABYTE_GA_G41M_COMBO
config MAX_CPUS int default 4
+# Override the default variant behavior, since the data.vbt is the same +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" + endif # BOARD_GIGABYTE_GA_G41M_ES2L diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name index e685ce1..efa4fa7 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_GIGABYTE_GA_G41M_ES2L bool "GA-G41M-ES2L" + +config BOARD_GIGABYTE_GA_G41M_COMBO + bool "GA-G41M-Combo" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/gpio.c b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/gpio.c new file mode 100644 index 0000000..1f5dfa0 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/gpio.c @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/hda_verb.c new file mode 100644 index 0000000..f4816ee --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/hda_verb.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0887, + 0x1458a002, // Subsystem ID + 0x0000000e, // Number of entries + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(2, 0x11, 0x411110f0), + AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c20), + AZALIA_PIN_CFG(2, 0x19, 0x02a19c30), + AZALIA_PIN_CFG(2, 0x1a, 0x0181342f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214c1f), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/overridetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/overridetree.cb new file mode 100644 index 0000000..d7cd61f --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/overridetree.cb @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/x4x # Northbridge + device domain 0 on # PCI domain + chip southbridge/intel/i82801gx # Southbridge + device pci 1f.0 on # ISA bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8720f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + irq 0xf0 = 0x00 + irq 0xf1 = 0x80 + end + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + io 0x62 = 0x000 + irq 0x70 = 7 + drq 0x74 = 4 + irq 0xf0 = 0x08 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + io 0x62 = 0x000 + irq 0x70 = 0x00 + irq 0xf0 = 0x80 + irq 0xf1 = 0x40 + irq 0xf2 = 0x0a + irq 0xf3 = 0x80 + irq 0xf4 = 0x80 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0xf0 = 0x48 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + irq 0x71 = 2 + irq 0xf0 = 0 + end + device pnp 2e.7 on end # GPIO (done in bootblock) + device pnp 2e.a off end # Consumer IR + end + end + end + end +end diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/superio.c b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/superio.c new file mode 100644 index 0000000..7aa4c2c --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-combo/superio.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <mainboard/superio.h> +#include <superio/ite/it8720f/it8720f.h> +#include <superio/ite/common/ite.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8720F_EC) + +void mainboard_early_superio(void) +{ + /* TODO: check this with datasheet */ + /* Set default GPIOs on superio */ + ite_reg_write(GPIO_DEV, 0x25, 0x50); + ite_reg_write(GPIO_DEV, 0x26, 0x0c); + ite_reg_write(GPIO_DEV, 0x27, 0x80); + ite_reg_write(GPIO_DEV, 0x28, 0x43); + ite_reg_write(GPIO_DEV, 0x29, 0x0a); + ite_reg_write(GPIO_DEV, 0x2c, 0x01); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_reg_write(GPIO_DEV, 0x73, 0x00); + ite_reg_write(GPIO_DEV, 0xb8, 0x40); + ite_reg_write(GPIO_DEV, 0xc0, 0x10); + ite_reg_write(GPIO_DEV, 0xc1, 0x0c); + ite_reg_write(GPIO_DEV, 0xc2, 0x80); + ite_reg_write(GPIO_DEV, 0xc3, 0x43); + ite_reg_write(GPIO_DEV, 0xc4, 0x0a); + ite_reg_write(GPIO_DEV, 0xc8, 0x00); + ite_reg_write(GPIO_DEV, 0xc9, 0x00); + ite_reg_write(GPIO_DEV, 0xcb, 0x42); + ite_reg_write(GPIO_DEV, 0xcc, 0x02); + ite_reg_write(GPIO_DEV, 0xf0, 0x10); + ite_reg_write(GPIO_DEV, 0xf1, 0x40); + ite_reg_write(GPIO_DEV, 0xf6, 0x0e); + + ite_reg_write(EC_DEV, 0xf0, 0x80); + ite_reg_write(EC_DEV, 0xf1, 0x40); + ite_reg_write(EC_DEV, 0xf2, 0x0a); + ite_reg_write(EC_DEV, 0xf3, 0x80); + ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 + ite_reg_write(EC_DEV, 0x30, 0x01); // Enable + + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ + ite_reg_write(GPIO_DEV, 0xEF, 0x7E); +}
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41868 )
Change subject: [WIP]mb/gigabyte/ga-g41m-combo: Add variant ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41868/2/src/mainboard/gigabyte/ga-g... File src/mainboard/gigabyte/ga-g41m-es2l/Kconfig:
https://review.coreboot.org/c/coreboot/+/41868/2/src/mainboard/gigabyte/ga-g... PS2, Line 46: # Override the default variant behavior, since the data.vbt is the same Shouldn't this be on the previous patchset?
Attention is currently required from: Arthur Heymans.
Cuno has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41868 )
Change subject: [WIP]mb/gigabyte/ga-g41m-combo: Add variant ......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2: Noticed this still says untested. I have been daily driving this board with Coreboot for 2 years. It is stable.
Attention is currently required from: Arthur Heymans.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41868 )
Change subject: [WIP]mb/gigabyte/ga-g41m-combo: Add variant ......................................................................
Patch Set 2: Code-Review+1
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Cuno (Code Review)