Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43892 )
Change subject: mb/libretrend/lt1000: Relocate devicetree FSP settings ......................................................................
mb/libretrend/lt1000: Relocate devicetree FSP settings
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I0a6454ad98bc7ad451641aee396027a4f2de773d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/libretrend/lt1000/devicetree.cb 1 file changed, 72 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/43892/1
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index dabef4b..2707df0 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -38,30 +38,11 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "0" - register "SataPortsDevSlp[2]" = "0" - register "SataSpeedLimit" = "2" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -130,23 +111,6 @@ .voltage_limit = 1520, }"
- register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - - register "PcieRpClkSrcNumber[0]" = "0" - register "PcieRpClkSrcNumber[3]" = "1" - register "PcieRpClkSrcNumber[4]" = "2" - register "PcieRpClkSrcNumber[8]" = "3" - register "PcieRpClkSrcNumber[9]" = "3" - register "PcieRpClkSrcNumber[10]" = "3" - register "PcieRpClkSrcNumber[11]" = "3" - - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # WiFi @@ -180,33 +144,85 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + + # FIXME: corresponding device entry is missing + register "Device4Enable" = "1" + device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA - device pci 1c.0 off end # PCI Express Port 1 + device pci 17.0 on # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + }" + register "SataPortsDevSlp" = "{ \ + [0] = 0, \ + [1] = 0, \ + [2] = 0, \ + }" + register "SataSpeedLimit" = "2" + end + + device pci 1c.0 off # PCI Express Port 1 + + # FIXME: RP is disabled + register "PcieRpClkSrcNumber[0]" = "0" + end device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 on end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.2 on # PCI Express Port 3 + register "PcieRpEnable[2]" = "1" + end + device pci 1c.3 off # PCI Express Port 4 + + # FIXME: RP is disabled + register "PcieRpEnable[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "1" + end device pci 1c.4 on # PCI Express Port 5 + register "PcieRpEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "2" smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X" end - device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.5 on end # PCI Express Port 6 FIXME: Port should be enabled? device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on # PCI Express Port 9 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "3" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "SSD_M.2 2242/2280" "SlotDataBusWidth4X" end - device pci 1d.1 on end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 + device pci 1d.1 on # PCI Express Port 10 + register "PcieRpEnable[9]" = "1" + register "PcieRpClkSrcNumber[9]" = "3" + end + device pci 1d.2 on # PCI Express Port 11 + register "PcieRpEnable[10]" = "1" + register "PcieRpClkSrcNumber[10]" = "3" + end + device pci 1d.3 on # PCI Express Port 12 + register "PcieRpEnable[11]" = "1" + register "PcieRpClkSrcNumber[11]" = "3" + end + + # eMMC is disabled + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + device pci 1f.0 on chip drivers/pc80/tpm device pnp 0c31.0 on end @@ -283,9 +299,17 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.3 on # Intel HDA + register "EnableAzalia" = "1" + end + device pci 1f.4 on # SMBus + register "SmbusEnable" = "1" + end device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 off # GbE + register "EnableLan" = "0" + end + + register "EnableTraceHub" = "0" end end
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43892 )
Change subject: mb/libretrend/lt1000: Relocate devicetree FSP settings ......................................................................
Patch Set 1: Code-Review+2
Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43892
to look at the new patch set (#2).
Change subject: mb/libretrend/lt1000: Relocate devicetree settings ......................................................................
mb/libretrend/lt1000: Relocate devicetree settings
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I0a6454ad98bc7ad451641aee396027a4f2de773d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/libretrend/lt1000/devicetree.cb 1 file changed, 72 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/43892/2
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43892 )
Change subject: mb/libretrend/lt1000: Relocate devicetree settings ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Felix Singer (Code Review)