Change in coreboot[master]: soc/amd/cezanne: add missing PM_ACPI_* bit definitions

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59588 )

Change subject: soc/amd/cezanne: add missing PM_ACPI_* bit definitions
......................................................................

soc/amd/cezanne: add missing PM_ACPI_* bit definitions

This part was copied from Picasso but Cezanne has some more bits used so
add the definitions now.

Signed-off-by: Felix Held 
Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59588
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
---
M src/soc/amd/cezanne/include/soc/southbridge.h
1 file changed, 16 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index b492088..3bba559 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -44,6 +44,7 @@
 #define   PM_ACPI_DECODE_STD		BIT(0)
 #define   PM_ACPI_GLOBAL_EN		BIT(1)
 #define   PM_ACPI_RTC_EN_EN		BIT(2)
+#define   PM_ACPI_SLPBTN_EN_EN		BIT(3)
 #define   PM_ACPI_TIMER_EN_EN		BIT(4)
 #define   PM_ACPI_MASK_ARB_DIS		BIT(6)
 #define   PM_ACPI_BIOS_RLS		BIT(7)
@@ -51,11 +52,26 @@
 #define   PM_ACPI_REDUCED_HW_EN		BIT(9)
 #define   PM_ACPI_S5_LPC_PIN_MODE_SEL	BIT(10)
 #define   PM_ACPI_S5_LPC_PIN_MODE	BIT(11)
+#define   PM_ACPI_LPC_RST_DIS		BIT(12)
+#define   PM_ACPI_SEL_PWRGD_PAD		BIT(13)
+#define   PM_ACPI_SEL_SMU_THERMTRIP	BIT(14)
+#define   PM_ACPI_SW_S5PWRMUX_OVRD_N	BIT(15)
+#define   PM_ACPI_SW_S5PWRMUX		BIT(16)
+#define   PM_ACPI_EN_SHUTDOWN_MSG	BIT(17)
+#define   PM_ACPI_EN_SYNC_FLOOD		BIT(18)
+#define   PM_ACPI_FORCE_SPIUSEPIN_0	BIT(19)
+#define   PM_ACPI_EN_DF_INTRWAKE	BIT(20)
+#define   PM_ACPI_MASK_USB_S5_RST	BIT(21)
+#define   PM_ACPI_USE_RSMU_RESET	BIT(22)
+#define   PM_ACPI_RST_USB_S5		BIT(23)
 #define   PM_ACPI_BLOCK_PCIE_PME	BIT(24)
 #define   PM_ACPI_PCIE_WAK_MASK		BIT(25)
+#define   PM_ACPI_PCIE_WAK_INTR_DIS	BIT(26)
 #define   PM_ACPI_WAKE_AS_GEVENT	BIT(27)
 #define   PM_ACPI_NB_PME_GEVENT		BIT(28)
 #define   PM_ACPI_RTC_WAKE_EN		BIT(29)
+#define   PM_ACPI_USE_GATED_ALINK_CLK	BIT(30)
+#define   PM_ACPI_DELAY_GPP_OFF_TIME	BIT(31)
 #define PM_SPI_PAD_PU_PD		0x90
 #define   PM_ESPI_CS_USE_DATA2		BIT(16)
 #define PM_LPC_GATING			0xec