Change in coreboot[master]: mb/asrock/h110m: fix SB-TSI address for SuperIO HWM

[Maxim Polyakov (Code Review)]

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35368 )

Change subject: mb/asrock/h110m: fix SB-TSI address for SuperIO HWM
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mb/asrock/h110m: fix SB-TSI address for SuperIO HWM

Fixes the SB-TSI base address value in the SuperIO hardware monitor
register. This value is got from a superiotool dump

Change-Id: I3aeb75bcf124a65dfebf3a8caa6ca150de617431
Signed-off-by: Maxim Polyakov 
---
M src/mainboard/asrock/h110m/devicetree.cb
1 file changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35368/1

diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index b4e6a02..5af5cfc 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -364,8 +364,10 @@
    			device pnp 2e.309 off end # GPIO5
    			device pnp 2e.a   off end # ACPI
    			device pnp 2e.b   on      # HWM, LED
+					# HM base address
    				io  0x60 = 0x0290
-					io  0x62 = 0
+					# SB-TSI base address
+					io  0x62 = 0x02a0
    				irq 0x70 = 0
    			end
    			device pnp 2e.d   off end # BCLK, WDT2, WDT_MEM

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35368 )

Change subject: mb/asrock/h110m: fix SB-TSI address for SuperIO HWM
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Patch Set 1: Code-Review+1

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35368 )

Change subject: mb/asrock/h110m: fix SB-TSI address for SuperIO HWM
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Patch Set 1:

wasn't SB-TSI something specific to AMD FCHs? haven't looked in the SIO datasheet if that is also used for something else on Intel platforms

[Maxim Polyakov (Code Review)]

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35368 )

Change subject: mb/asrock/h110m: fix SB-TSI address for SuperIO HWM
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Patch Set 1:
> Patch Set 1:

Thanks for the review
> wasn't SB-TSI something specific to AMD FCHs? haven't looked in the SIO datasheet if that is also used for something else on Intel platforms

Yes you are right. Temperature Sensor Interface is used only with AMD processors.
Probably the AMI firmware configures all possible interfaces in the SuperIO.
This is confusing for me

[Maxim Polyakov (Code Review)]

Maxim Polyakov has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35368 )

Change subject: mb/asrock/h110m: fix SB-TSI address for SuperIO HWM
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Abandoned

These changes are not required for boards with Intel processors