Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP power sequence adjust
Hello Chris Wang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/48863
to review the following change.
Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust ......................................................................
soc/amd/picasso: Add UPDs for support eDP power sequence adjust
Add UPDs for eDP power sequence adjust.
BUG=b:171954512 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289 --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 19 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/48863/1
diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 48bd35f..015778d 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -40,16 +40,25 @@ /** Offset 0x0128**/ uint8_t gnb_ioapic_id; /** Offset 0x0129**/ uint8_t fch_ioapic_id; /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; - /** Offset 0x0130**/ uint8_t unused4[16]; - /** Offset 0x0140**/ uint8_t DpPhyOverride; - /** Offset 0x0141**/ uint16_t EDpPhySel; - /** Offset 0x0143**/ uint8_t EDpVersion; - /** Offset 0x0144**/ uint8_t EDpTableSize; - /** Offset 0x0145**/ uint8_t DpVsPemphLevel; - /** Offset 0x0146**/ uint16_t MarginDeemPh; - /** Offset 0x0148**/ uint8_t Deemph6db4; - /** Offset 0x0149**/ uint8_t BoostAdj; - /** Offset 0x014A**/ uint8_t UnusedUpdSpace1[6]; + /** Offset 0x0130**/ uint8_t unused4; + /** Offset 0x0131**/ uint8_t DpPhyOverride; + /** Offset 0x0132**/ uint16_t EDpPhySel; + /** Offset 0x0134**/ uint8_t EDpVersion; + /** Offset 0x0135**/ uint8_t EDpTableSize; + /** Offset 0x0136**/ uint8_t DpVsPemphLevel; + /** Offset 0x0137**/ uint16_t MarginDeemPh; + /** Offset 0x0139**/ uint8_t Deemph6db4; + /** Offset 0x013A**/ uint8_t BoostAdj; + /** Offset 0x013B**/ uint16_t backlight_pwmhz; + /** Offset 0x013D**/ uint8_t pwron_digon_to_De; + /** Offset 0x013E**/ uint8_t pwron_de_to_varybl; + /** Offset 0x013F**/ uint8_t pwrdown_varybloff_to_de; + /** Offset 0x0140**/ uint8_t pwrdown_de_to_digoff; + /** Offset 0x0141**/ uint8_t pwroff_delay; + /** Offset 0x0142**/ uint8_t pwron_varybl_to_blon; + /** Offset 0x0143**/ uint8_t pwrdown_bloff_to_varybloff; + /** Offset 0x0144**/ uint8_t min_allowed_bl_level; + /** Offset 0x0145**/ uint8_t UnusedUpdSpace1[11]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG;
Attention is currently required from: chris wang. Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48863 )
Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust ......................................................................
Patch Set 4:
(1 comment)
File src/vendorcode/amd/fsp/picasso/FspsUpd.h:
https://review.coreboot.org/c/coreboot/+/48863/comment/863bb997_7dc9218a PS4, Line 53: /** Offset 0x013D**/ uint8_t pwron_digon_to_De; Perhaps pwron_digon_to_de?
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Chris Wang, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48863
to look at the new patch set (#6).
Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust ......................................................................
soc/amd/picasso: Add UPDs for support eDP power sequence adjust
Add UPDs for eDP power sequence adjust.
BUG=b:171954512 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289 --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 19 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/48863/6
Attention is currently required from: Nikolai Vyssotski. chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48863 )
Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust ......................................................................
Patch Set 6:
(1 comment)
File src/vendorcode/amd/fsp/picasso/FspsUpd.h:
https://review.coreboot.org/c/coreboot/+/48863/comment/951218f1_460670c2 PS4, Line 53: /** Offset 0x013D**/ uint8_t pwron_digon_to_De;
Perhaps pwron_digon_to_de?
Done
Attention is currently required from: Furquan Shaikh, Kangheui Won, chris wang. Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48863 )
Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust ......................................................................
Patch Set 8: Code-Review+1
Attention is currently required from: Furquan Shaikh, Kangheui Won, chris wang. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48863 )
Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust ......................................................................
Patch Set 8: Code-Review+2
Attention is currently required from: Furquan Shaikh, Kangheui Won. Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Kangheui Won, Nikolai Vyssotski, Chris Wang, EricR Lai, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48863
to look at the new patch set (#9).
Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust ......................................................................
soc/amd/picasso: Add UPDs for support eDP power sequence adjust
Add UPDs for eDP power sequence adjust.
BUG=b:171954512 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289 --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 19 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/48863/9
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48863 )
Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust ......................................................................
soc/amd/picasso: Add UPDs for support eDP power sequence adjust
Add UPDs for eDP power sequence adjust.
BUG=b:171954512 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48863 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 19 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Nikolai Vyssotski: Looks good to me, but someone else must approve
diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 48bd35f..ee516f8 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -40,16 +40,25 @@ /** Offset 0x0128**/ uint8_t gnb_ioapic_id; /** Offset 0x0129**/ uint8_t fch_ioapic_id; /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; - /** Offset 0x0130**/ uint8_t unused4[16]; - /** Offset 0x0140**/ uint8_t DpPhyOverride; - /** Offset 0x0141**/ uint16_t EDpPhySel; - /** Offset 0x0143**/ uint8_t EDpVersion; - /** Offset 0x0144**/ uint8_t EDpTableSize; - /** Offset 0x0145**/ uint8_t DpVsPemphLevel; - /** Offset 0x0146**/ uint16_t MarginDeemPh; - /** Offset 0x0148**/ uint8_t Deemph6db4; - /** Offset 0x0149**/ uint8_t BoostAdj; - /** Offset 0x014A**/ uint8_t UnusedUpdSpace1[6]; + /** Offset 0x0130**/ uint8_t unused4; + /** Offset 0x0131**/ uint8_t DpPhyOverride; + /** Offset 0x0132**/ uint16_t EDpPhySel; + /** Offset 0x0134**/ uint8_t EDpVersion; + /** Offset 0x0135**/ uint8_t EDpTableSize; + /** Offset 0x0136**/ uint8_t DpVsPemphLevel; + /** Offset 0x0137**/ uint16_t MarginDeemPh; + /** Offset 0x0139**/ uint8_t Deemph6db4; + /** Offset 0x013A**/ uint8_t BoostAdj; + /** Offset 0x013B**/ uint16_t backlight_pwmhz; + /** Offset 0x013D**/ uint8_t pwron_digon_to_de; + /** Offset 0x013E**/ uint8_t pwron_de_to_varybl; + /** Offset 0x013F**/ uint8_t pwrdown_varybloff_to_de; + /** Offset 0x0140**/ uint8_t pwrdown_de_to_digoff; + /** Offset 0x0141**/ uint8_t pwroff_delay; + /** Offset 0x0142**/ uint8_t pwron_varybl_to_blon; + /** Offset 0x0143**/ uint8_t pwrdown_bloff_to_varybloff; + /** Offset 0x0144**/ uint8_t min_allowed_bl_level; + /** Offset 0x0145**/ uint8_t UnusedUpdSpace1[11]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG;
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chris wang (Code Review) -
EricR Lai (Code Review)
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Nikolai Vyssotski (Code Review)
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Patrick Georgi (Code Review)