Ashish Kumar Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81959?usp=email )
Change subject: arch/x86: Update X86_64 memcpy for 4 byte copy ......................................................................
arch/x86: Update X86_64 memcpy for 4 byte copy
The current 8 byte copy cannot write to spi flash, due to 4 byte limit. This affected MRC Cache R/W in X86_64. Hence update to 4 byte copy.
BUG=None TEST=Build and boot google/rex 64-bit and verified MRC cache working.
Change-Id: I1110cc18f5aa59c864e3cc04b9e6b3501ec4d54d Signed-off-by: Ashish Kumar Mishra ashish.k.mishra@intel.com --- M src/arch/x86/memcpy.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/81959/1
diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c index 9da2a75..9f6f1af 100644 --- a/src/arch/x86/memcpy.c +++ b/src/arch/x86/memcpy.c @@ -16,11 +16,11 @@
#if ENV_X86_64 asm volatile( - "rep ; movsq\n\t" - "mov %4,%%rcx\n\t" + "rep ; movsd\n\t" + "mov %4, %%rcx\n\t" "rep ; movsb\n\t" : "=&c" (d0), "=&D" (d1), "=&S" (d2) - : "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src) + : "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src) : "memory" ); #else