Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83773?usp=email )
Change subject: soc/amd/common/include/spi: add and use SPI_MISC_CNTRL define ......................................................................
soc/amd/common/include/spi: add and use SPI_MISC_CNTRL define
This register is currently used by the SPI DMA code that sets an undocumented bit. A later patch will add and use some other bit in this register.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I48447dcfb3cee07619a9b42434731f0b21458021 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83773 Reviewed-by: Matt DeVillier matt.devillier@amd.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/lpc/spi_dma.c 2 files changed, 4 insertions(+), 2 deletions(-)
Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index cf91814..babe635 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -76,6 +76,8 @@ #define SPI_FIFO_LAST_BYTE 0xc6 /* 0xc7 for Cezanne */ #define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1)
+#define SPI_MISC_CNTRL 0xfc + struct spi_config { /* * Default values if not overridden by mainboard: diff --git a/src/soc/amd/common/block/lpc/spi_dma.c b/src/soc/amd/common/block/lpc/spi_dma.c index 701b61a..9ff9b0e 100644 --- a/src/soc/amd/common/block/lpc/spi_dma.c +++ b/src/soc/amd/common/block/lpc/spi_dma.c @@ -277,9 +277,9 @@ static void spi_dma_fix(void) { /* Internal only registers */ - uint8_t val = spi_read8(0xfc); + uint8_t val = spi_read8(SPI_MISC_CNTRL); val |= BIT(6); - spi_write8(0xfc, val); + spi_write8(SPI_MISC_CNTRL, val); }
void boot_device_init(void)