Change in coreboot[master]: soc/amd/common: move FCH IOAPIC and HPET init from SMBUs to LPC device

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58334 )

Change subject: soc/amd/common: move FCH IOAPIC and HPET init from SMBUs to LPC device
......................................................................

soc/amd/common: move FCH IOAPIC and HPET init from SMBUs to LPC device

Despite the SMBus device being function 0 of the FCH PCI device, the
MMIO resource of the FCH IOAPIC is on the LPC device which is function 3
of the same PCI device, so move the FCH IOAPIC initialization code to
the LPC device. Since the HPET was enabled in the same function, also
move it to the LPC device initialization.

TEST=On Mandolin both IOAPICs are still correctly detected by Linux.

Signed-off-by: Felix Held 
Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334
Reviewed-by: Fred Reitberger 
Reviewed-by: Marshall Dawson 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/smbus/sm.c
2 files changed, 11 insertions(+), 10 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved
  Fred Reitberger: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 99f84fa..60c85b9 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <arch/ioapic.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -15,6 +16,7 @@
 #include <amdblocks/acpi.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/espi.h>
+#include <amdblocks/ioapic.h>
 #include <amdblocks/lpc.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
@@ -34,6 +36,12 @@
    pm_write8(PM_SERIRQ_CONF, byte);
 }

+static void fch_ioapic_init(void)
+{
+	fch_enable_ioapic_decode();
+	setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID);
+}
+
 static void lpc_init(struct device *dev)
 {
    u8 byte;
@@ -83,6 +91,9 @@
    setup_i8254();

setup_serirq();
+
+	fch_ioapic_init();
+	fch_configure_hpet();
 }

static void lpc_read_resources(struct device *dev)
diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c
index e8b7c0f..801a154 100644
--- a/src/soc/amd/common/block/smbus/sm.c
+++ b/src/soc/amd/common/block/smbus/sm.c
@@ -1,20 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <amdblocks/acpimmio.h>
-#include <amdblocks/ioapic.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/smbus.h>
 #include <device/smbus_host.h>
-#include <arch/ioapic.h>
-
-static void sm_init(struct device *dev)
-{
-	fch_enable_ioapic_decode();
-	setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID);
-	fch_configure_hpet();
-}

static u32 get_sm_mmio(struct device *dev)
 {
@@ -77,7 +68,6 @@
    .read_resources		= noop_read_resources,
    .set_resources		= noop_set_resources,
    .enable_resources	= pci_dev_enable_resources,
-	.init			= sm_init,
    .scan_bus		= scan_smbus,
    .ops_pci		= &pci_dev_ops_pci,
    .ops_smbus_bus		= &lops_smbus_bus,