Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 )
Change subject: mb/kontron: Add Kontron mAL10 COMe module support ......................................................................
Patch Set 54:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal1... File src/mainboard/kontron/mal10/acpi/cpld.asl:
https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal1... PS48, Line 15: 0x00
0
Done
https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal1... PS48, Line 16: 0x01
2
Done
https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal1... File src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c:
https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal1... PS48, Line 9: /* GPIO_0 - GPIO (DW0: 0x44000300, DW1: 0x0003d000) */
Unless you have access to schematics/boardviews, please drop these comments.
Done
https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal1... File src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal1... PS48, Line 9: # Configure CLKREQ of PCIe root ports : register "pcie_rp_clkreq_pin[0]" = "1" : register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" : register "pcie_rp_clkreq_pin[2]" = "0" : register "pcie_rp_clkreq_pin[3]" = "0" : register "pcie_rp_clkreq_pin[4]" = "0" : register "pcie_rp_clkreq_pin[5]" = "0"
Carriers should also control which PCIe root ports are enabled. […]
Done
https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal1... File src/mainboard/kontron/mal10/variants/mal10/gpio.c:
https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal1... PS48, Line 9: /* GPIO_97 - FST_SPI_CS0_N (DW0: 0x44000502, DW1: 0x00003c00) */
Same as other gpio. […]
Done
-
Maxim Polyakov (Code Review)