[XS] Change in coreboot[master]: mb/google/rex: enable d3hot for storage devices

[Sukumar Ghorai (Code Review)]

Attention is currently required from: Kangheui Won.

Hello Kangheui Won,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/76835?usp=email

to review the following change.

Change subject: mb/google/rex: enable d3hot for storage devices
......................................................................

mb/google/rex: enable d3hot for storage devices

_DSD "StorageD3Enable" property is needed to set under the root port in
the DSDT or SSDT. The ACPI _DSD method is the preferred way to opt
D3hot support for storage devices.

Name (_DSD, Package () {
          ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"),
            Package () {
                Package (2) {"StorageD3Enable", 1}, // 1 - Enable; 0 - Disable
            }
        }
    )

BUG=b:289028958
TEST=Check code compiles & boot rex, and verify the "StorageD3Enable"
SSDT entry.

Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7
Signed-off-by: Kangheui Won 
Signed-off-by: Sukumar Ghorai 
---
M src/mainboard/google/rex/variants/rex0/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/76835/1

diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 793a46d..1435a7b 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -302,6 +302,13 @@
    			.clk_req = 4,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
+				register "srcclk_pin" = "4"
+				device generic 0 on end
+			end
    	end	#PCIE9 SSD card
    	device ref ish on
    		probe ISH ISH_ENABLE