Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68584 )
Change subject: soc/amd: Define AMD_FWM_POSITION config item ......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/common/block/psp/Kconfig:
https://review.coreboot.org/c/coreboot/+/68584/comment/ee15ea25_b76b32a5 PS4, Line 87: default 0xFFFA0000 if AMD_FWM_POSITION_INDEX = 0 : default 0xFFF20000 if AMD_FWM_POSITION_INDEX = 1 : default 0xFFE20000 if AMD_FWM_POSITION_INDEX = 2 : default 0xFFC20000 if AMD_FWM_POSITION_INDEX = 3 : default 0xFF820000 if AMD_FWM_POSITION_INDEX = 4 : default 0xFF020000 if AMD_FWM_POSITION_INDEX = 5
Unfortunately amdfwtool expects it to be x86 memory mapped space. There seems to be an assumption that the the last 16MB (0xff000000 - 0xffffffff) in the x86 32 bit memory map is where the SPI flash is present even if it's size is 16 MB or not. So it has to be an offset in that 16 MB. I will look for a best way to change it.
That is not true. Only MIN(16MB, CONFIG_ROM_SIZE) gets mapped. The PSP looks for the cookie on fixed addresses in flash space: 0x20000, 0x820000, 0xC20000, 0xE20000, 0xF20000, 0xFA0000. Where that is in memory map depends therefore on CONFIG_ROM_SIZE.
We also need to look ahead to 32 & 64MiB flash sizes and mapping the flash to the area over 4GiB so that we can access more than 16MiB at a time. That would also mean 64-bit coreboot builds.
Obviously those are both larger tasks and not needed yet, though they might be needed on Morgana or Glinda platforms.
Only 16MB gets memory mapped. When the flash size is for instance 32M, only the lower (by default) or the upper part of the flash gets memory mapped.
-
Arthur Heymans (Code Review)