Change in coreboot[master]: soc/intel/cnl: Configure PcieRpSlotImplemented

[Felix Singer (Code Review)]

Hello Nico Huber,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/39986

to review the following change.

Change subject: soc/intel/cnl: Configure PcieRpSlotImplemented
......................................................................

soc/intel/cnl: Configure PcieRpSlotImplemented

Default was probably the opposite, so all devicetrees would need an
update.

Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/39986/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 7794fd4..563e13f 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -187,6 +187,8 @@
    uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
    /* PCIe LTR(Latency Tolerance Reporting) mechanism */
    uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
+	/* Implemented as slot or built-in? */
+	uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
    /* Enable/Disable HotPlug support for Root Port */
    uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 4634806..c35d21b 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -330,6 +330,8 @@
           sizeof(config->PcieClkSrcClkReq));
    memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
           sizeof(config->PcieRpLtrEnable));
+	memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented,
+	       sizeof(config->PcieRpSlotImplemented));
    memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
           sizeof(config->PcieRpHotPlug));

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure PcieRpSlotImplemented
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39986/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39986/2//COMMIT_MSG@10 
PS2, Line 10: update.
Maybe we could tie it to `smbios_slot_type` in `struct device`, or add
another flag into `struct device`? Having yet another FSP setting in
the devicetree that gets redundant information seems wrong...

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure PcieRpSlotImplemented
......................................................................

Patch Set 2: Code-Review+1

[Christian Walter (Code Review)]

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure PcieRpSlotImplemented
......................................................................

Patch Set 2:

What difference does it make?

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure PcieRpSlotImplemented
......................................................................

Patch Set 2:
> What difference does it make?

Well, first of all it sets the SI bit of the RP PCI device. That can
influence any software acting on that bit. I just read a comment that
it also enables the PDS (present detect state?) otherwise it might be
stuck at 1, idk. IIRC, FSP runs a timeout for all RPs that implement
a slot at once to detect presence of downstream devices. There maybe
more that I don't recall atm or just don't know ;)

[Christian Walter (Code Review)]

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure PcieRpSlotImplemented
......................................................................

Patch Set 2:
> Patch Set 2:
> > What difference does it make?
>
> Well, first of all it sets the SI bit of the RP PCI device. That can
> influence any software acting on that bit. I just read a comment that
> it also enables the PDS (present detect state?) otherwise it might be
> stuck at 1, idk. IIRC, FSP runs a timeout for all RPs that implement
> a slot at once to detect presence of downstream devices. There maybe
> more that I don't recall atm or just don't know ;)

Thanks for clearing this up for me :)

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure PcieRpSlotImplemented
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39986/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39986/7//COMMIT_MSG@9 
PS7, Line 9: Default was probably the opposite, so all devicetrees would need an
huh? probably? opposite of what?
default is 0x1 for all ports, according to fsp bsf, so yes, the devicetrees need to be updated

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure PcieRpSlotImplemented
......................................................................

Patch Set 7: Code-Review+1

[Felix Singer (Code Review)]

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure PcieRpSlotImplemented
......................................................................

Set Ready For Review

Change in coreboot[master]: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

[Felix Singer (Code Review)]

Hello build bot (Jenkins), Nico Huber, Jeremy Soller, Angel Pons, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39986

to look at the new patch set (#11).

Change subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
......................................................................

soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.

Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber 
Signed-off-by: Felix Singer 
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/hatch/variants/duffy/overridetree.cb
M src/mainboard/google/hatch/variants/faffy/overridetree.cb
M src/mainboard/google/hatch/variants/kaisa/overridetree.cb
M src/mainboard/google/hatch/variants/noibat/overridetree.cb
M src/mainboard/google/hatch/variants/puff/overridetree.cb
M src/mainboard/google/hatch/variants/wyvern/overridetree.cb
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
M src/mainboard/purism/librem_whl/devicetree.cb
M src/mainboard/system76/lemp9/devicetree.cb
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
21 files changed, 153 insertions(+), 44 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/39986/11

Change in coreboot[master]: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
......................................................................

Patch Set 11: Code-Review+2

Change in coreboot[master]: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

[Felix Singer (Code Review)]

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
......................................................................

Patch Set 11:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39986/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39986/7//COMMIT_MSG@9 
PS7, Line 9: Default was probably the opposite, so all devicetrees would need an
> huh? probably? opposite of what? […]

Updated all related devicetrees.

Change in coreboot[master]: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

[Felix Singer (Code Review)]

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
......................................................................

Patch Set 11:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39986/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39986/2//COMMIT_MSG@10 
PS2, Line 10: update.
> Maybe we could tie it to `smbios_slot_type` in `struct device`, or add […]

Done

Change in coreboot[master]: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

[Felix Singer (Code Review)]

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
......................................................................

Set Ready For Review

Change in coreboot[master]: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
......................................................................

Patch Set 12: Code-Review+2

Change in coreboot[master]: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

[Felix Singer (Code Review)]

Hello build bot (Jenkins), Nico Huber, Jeremy Soller, Angel Pons, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39986

to look at the new patch set (#15).

Change subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
......................................................................

soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.

Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber 
Signed-off-by: Felix Singer 
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/hatch/variants/duffy/overridetree.cb
M src/mainboard/google/hatch/variants/faffy/overridetree.cb
M src/mainboard/google/hatch/variants/kaisa/overridetree.cb
M src/mainboard/google/hatch/variants/noibat/overridetree.cb
M src/mainboard/google/hatch/variants/puff/overridetree.cb
M src/mainboard/google/hatch/variants/wyvern/overridetree.cb
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
M src/mainboard/purism/librem_whl/devicetree.cb
M src/mainboard/system76/lemp9/devicetree.cb
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
23 files changed, 171 insertions(+), 50 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/39986/15

Change in coreboot[master]: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

[Felix Singer (Code Review)]

Hello build bot (Jenkins), Nico Huber, Jeremy Soller, Angel Pons, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39986

to look at the new patch set (#16).

Change subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
......................................................................

soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.

Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber 
Signed-off-by: Felix Singer 
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/hatch/variants/duffy/overridetree.cb
M src/mainboard/google/hatch/variants/faffy/overridetree.cb
M src/mainboard/google/hatch/variants/kaisa/overridetree.cb
M src/mainboard/google/hatch/variants/noibat/overridetree.cb
M src/mainboard/google/hatch/variants/puff/overridetree.cb
M src/mainboard/google/hatch/variants/wyvern/overridetree.cb
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
M src/mainboard/purism/librem_whl/devicetree.cb
M src/mainboard/system76/lemp9/devicetree.cb
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
23 files changed, 171 insertions(+), 50 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/39986/16

Change in coreboot[master]: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
......................................................................

Patch Set 16: Code-Review+2

Change in coreboot[master]: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
......................................................................

soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.

Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber 
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/hatch/variants/duffy/overridetree.cb
M src/mainboard/google/hatch/variants/faffy/overridetree.cb
M src/mainboard/google/hatch/variants/kaisa/overridetree.cb
M src/mainboard/google/hatch/variants/noibat/overridetree.cb
M src/mainboard/google/hatch/variants/puff/overridetree.cb
M src/mainboard/google/hatch/variants/wyvern/overridetree.cb
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
M src/mainboard/purism/librem_whl/devicetree.cb
M src/mainboard/system76/lemp9/devicetree.cb
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
23 files changed, 171 insertions(+), 50 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 4011693..851248d 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -444,12 +444,14 @@
    	device pci 1c.7 off end # PCI Express Port 8
    	device pci 1d.0 on
    		smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
+			register "PcieRpSlotImplemented[8]" = "1"
    	end # PCI Express Port 9
    	device pci 1d.1 off  end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off  end # PCI Express Port 12
    	device pci 1d.4 on
    		smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[12]" = "1"
    	end # PCI Express Port 13 (x4)
    	device pci 1e.0 on end # UART #0
    	device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index a12b71c..f13fcf8 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -329,7 +329,9 @@
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
    	device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9 (X4 NVME)
+		device pci 1d.0 on	# PCI Express Port 9 (X4 NVME)
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
    	device pci 1d.1 off end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
@@ -339,6 +341,7 @@
    			register "wake" = "GPE0_DW1_01"
    			device pci 00.0 on  end
    		end
+			register "PcieRpSlotImplemented[13]" = "1"
    	end # PCI Express Port 14 (x4)
    	device pci 1e.0 on  end # UART #0
    	device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
index 7f75c78..10da161 100644
--- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
@@ -394,8 +394,11 @@
    			register "device_index" = "0"
    			device pci 00.0 on end
    		end
+			register "PcieRpSlotImplemented[6]" = "1"
    	end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
    	device pci 1e.3 off end # GSPI #1
    end

diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
index c1c44a6..61c7f0f 100644
--- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
@@ -401,8 +401,11 @@
    			register "device_index" = "0"
    			device pci 00.0 on end
    		end
+			register "PcieRpSlotImplemented[6]" = "1"
    	end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
    	device pci 1e.3 off end # GSPI #1
    end

diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
index 67e62e7..dbf1851 100644
--- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
@@ -394,8 +394,11 @@
    			register "device_index" = "0"
    			device pci 00.0 on end
    		end
+			register "PcieRpSlotImplemented[6]" = "1"
    	end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
    	device pci 1e.3 off end # GSPI #1
    end

diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb
index 2de90ec..c73798a 100644
--- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb
@@ -309,8 +309,11 @@
    			register "device_index" = "0"
    			device pci 00.0 on end
    		end
+			register "PcieRpSlotImplemented[6]" = "1"
    	end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
    	device pci 1e.3 off end # GSPI #1
    end

diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index 7ead982..a5aa702 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -333,8 +333,11 @@
    			register "device_index" = "0"
    			device pci 00.0 on end
    		end
+			register "PcieRpSlotImplemented[6]" = "1"
    	end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
    	device pci 1e.3 off end # GSPI #1
    end

diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
index d7b2298..3d5da00 100644
--- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
@@ -328,8 +328,11 @@
    			register "device_index" = "0"
    			device pci 00.0 on end
    		end
+			register "PcieRpSlotImplemented[6]" = "1"
    	end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
    	device pci 1e.3 off end # GSPI #1
    end

diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index bacc6dc..760e351 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -377,8 +377,11 @@
    	device pci 1d.0 off end # PCI Express Port 9
    	device pci 1d.1 on
    		smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
+			register "PcieRpSlotImplemented[9]" = "1"
    	end # PCI Express Port 10
-		device pci 1d.2 on  end # PCI Express Port 11
+		device pci 1d.2 on	# PCI Express Port 11
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
    	device pci 1d.3 off end # PCI Express Port 12
    	device pci 1d.4 on
    		chip drivers/generic/bayhub
@@ -386,6 +389,7 @@
    			device pci 00.0 on end
    		end
    		smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[12]" = "1"
    	end # PCI Express Port 13 (x4)
    	device pci 1e.0 off end # UART #0
    	device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index e79a8a5..78f024c 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -385,22 +385,29 @@
    	device pci 19.1 off end # I2C #5
    	device pci 19.2 on  end # UART #2
    	device pci 1a.0 off end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 (USB)
+		device pci 1c.0 on	# PCI Express Port 1 (USB)
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
    	device pci 1c.1 off end # PCI Express Port 2 (USB)
    	device pci 1c.2 off end # PCI Express Port 3 (USB)
    	device pci 1c.3 off end # PCI Express Port 4 (USB)
    	device pci 1c.4 off end # PCI Express Port 5 (USB)
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 on  end # PCI Express Port 8
+		device pci 1c.7 on	# PCI Express Port 8
+			register "PcieRpSlotImplemented[7]" = "1"
+		end
    	device pci 1d.0 on
    		chip drivers/generic/bayhub
    			register "power_saving" = "1"
    			device pci 00.0 on end
    		end
    		smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
+			register "PcieRpSlotImplemented[8]" = "1"
    	end # PCI Express Port 9
-		device pci 1d.1 on  end # PCI Express Port 10
+		device pci 1d.1 on	# PCI Express Port 10
+			register "PcieRpSlotImplemented[9]" = "1"
+		end
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
    	device pci 1d.4 on
@@ -409,6 +416,7 @@
    			device pci 00.0 on end
    		end
    		smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[12]" = "1"
    	end # PCI Express Port 13 (x4)
    	device pci 1e.0 off end # UART #0
    	device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index e5f867c..f24e191 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -124,12 +124,18 @@
    	device pci 19.1 off end # I2C #5
    	device pci 19.2 on  end # UART #2
    	device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
    	device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
    	device pci 1d.1 off end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 53c677b..6f282f0 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -140,12 +140,18 @@
    	device pci 19.1 off end # I2C #5
    	device pci 19.2 on  end # UART #2
    	device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
    	device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
    	device pci 1d.1 off end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
index 989b5cd..a145584 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
@@ -99,12 +99,18 @@
    	device pci 19.1 off end # I2C #5 (Not available on PCH-H)
    	device pci 19.2 on  end # UART #2
    	device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
    	device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
    	device pci 1d.4 off end # PCI Express Port 13
    	device pci 1d.5 off end # PCI Express Port 14
    	device pci 1d.6 off end # PCI Express Port 15
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
index a63d4c0..a876994 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
@@ -107,12 +107,18 @@
    	device pci 19.1 off end # I2C #5 (Not available on PCH-H)
    	device pci 19.2 on  end # UART #2
    	device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1
-		device pci 1c.4 on  end # PCI Express Port 5
+		device pci 1c.0 on	# PCI Express Port 1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
    	device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9 x4 SLOT 1
+		device pci 1d.0 on	# PCI Express Port 9 x4 SLOT 1
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
    	device pci 1d.1 off end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
@@ -120,11 +126,21 @@
    	device pci 1d.5 off end # PCI Express Port 14
    	device pci 1d.6 off end # PCI Express Port 15
    	device pci 1d.7 off end # PCI Express Port 16
-		device pci 1b.0 on  end # PCI Express Port 17
-		device pci 1b.1 on  end # PCI Express Port 18
-		device pci 1b.2 on  end # PCI Express Port 19
-		device pci 1b.3 on  end # PCI Express Port 20
-		device pci 1b.4 on  end # PCI Express Port 21 X4 SLOT 2
+		device pci 1b.0 on	# PCI Express Port 17
+			register "PcieRpSlotImplemented[16]" = "1"
+		end
+		device pci 1b.1 on	# PCI Express Port 18
+			register "PcieRpSlotImplemented[17]" = "1"
+		end
+		device pci 1b.2 on	# PCI Express Port 19
+			register "PcieRpSlotImplemented[18]" = "1"
+		end
+		device pci 1b.3 on	# PCI Express Port 20
+			register "PcieRpSlotImplemented[19]" = "1"
+		end
+		device pci 1b.4 on	# PCI Express Port 21 X4 SLOT 2
+			register "PcieRpSlotImplemented[20]" = "1"
+		end
    	device pci 1e.1 off end # UART #1
    	device pci 1f.6 on  end # GbE
    end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
index c5c291d..f48c9b4 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
@@ -84,12 +84,18 @@
    	device pci 19.1 off end # I2C #5
    	device pci 19.2 on  end # UART #2
    	device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
    	device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
    	device pci 1d.1 off end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
index a8f6766..28b33cf 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
@@ -94,12 +94,18 @@
    	device pci 19.1 off end # I2C #5
    	device pci 19.2 on  end # UART #2
    	device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
    	device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
    	device pci 1d.1 off end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
index 1e38824..89d6036 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
@@ -78,12 +78,18 @@
    	device pci 19.1 off end # I2C #5
    	device pci 19.2 on  end # UART #2
    	device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
    	device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
    	device pci 1d.1 off end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb
index a89ba1b..cae3d4c 100644
--- a/src/mainboard/prodrive/hermes/devicetree.cb
+++ b/src/mainboard/prodrive/hermes/devicetree.cb
@@ -35,6 +35,7 @@
    		device pci 00.0 on      # Aspeed PCI Bridge
    			device pci 00.0 on end  # Aspeed 2500 VGA
    		end
+			register "PcieRpSlotImplemented[14]" = "1"
    	end
    	device pci 1f.0 on	# LPC Interface
    		chip drivers/pc80/tpm
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
index 8098c56..7759b57 100644
--- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
@@ -183,20 +183,35 @@
    	end
    	device pci 1b.4 on	# PCIe root port 21 (Slot 1)
    		smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[20]" = "1"
    	end
    	device pci 1c.0 on	# PCIe root port 1 (Slot 3)
    		smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[0]" = "1"
    	end
-		device pci 1c.4 on end # PCIe root port 5 (PHY 3)
-		device pci 1c.5 on end # PCIe root port 6 (PHY 4)
-		device pci 1c.6 on end # PCIe root port 7 (PHY 2)
-		device pci 1c.7 on end # PCIe root port 8 (PHY 1)
+		device pci 1c.4 on	# PCIe root port 5 (PHY 3)
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
+		device pci 1c.5 on	# PCIe root port 6 (PHY 4)
+			register "PcieRpSlotImplemented[5]" = "1"
+		end
+		device pci 1c.6 on	# PCIe root port 7 (PHY 2)
+			register "PcieRpSlotImplemented[6]" = "1"
+		end
+		device pci 1c.7 on	# PCIe root port 8 (PHY 1)
+			register "PcieRpSlotImplemented[7]" = "1"
+		end

device pci 1d.0 on	# PCIe root port 9 (M2 M)
    		smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[8]" = "1"
    	end
-		device pci 1d.5 on end # PCIe root port 14 (PHY 0)
-		device pci 1d.6 on end # PCIe root port 15 (BMC)
+		device pci 1d.5 on	# PCIe root port 14 (PHY 0)
+			register "PcieRpSlotImplemented[13]" = "1"
+		end
+		device pci 1d.6 on	# PCIe root port 15 (BMC)
+			register "PcieRpSlotImplemented[14]" = "1"
+		end

device pci 1e.0 on  end # UART #0
    	device pci 1e.1 on  end # UART #1
diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb
index c122bb8..fc3f418 100644
--- a/src/mainboard/purism/librem_whl/devicetree.cb
+++ b/src/mainboard/purism/librem_whl/devicetree.cb
@@ -293,12 +293,18 @@
    	device pci 1c.4 off end # PCI Express Port 5
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 on  end # PCI Express Port 8  (WLAN)
+		device pci 1c.7 on	# PCI Express Port 8  (WLAN)
+			register "PcieRpSlotImplemented[7]" = "1"
+		end
    	device pci 1d.0 off end # PCI Express Port 9
-		device pci 1d.1 on  end # PCI Express Port 10 (LAN)
+		device pci 1d.1 on	# PCI Express Port 10 (LAN)
+			register "PcieRpSlotImplemented[9]" = "1"
+		end
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 on  end # PCI Express Port 13 (NVMe)
+		device pci 1d.4 on	# PCI Express Port 13 (NVMe)
+			register "PcieRpSlotImplemented[12]" = "1"
+		end
    	device pci 1d.5 off end # PCI Express Port 14
    	device pci 1d.6 off end # PCI Express Port 15
    	device pci 1d.7 off end # PCI Express Port 16
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb
index 9cdeeab..659ca89 100644
--- a/src/mainboard/system76/lemp9/devicetree.cb
+++ b/src/mainboard/system76/lemp9/devicetree.cb
@@ -215,14 +215,22 @@
    	device pci 1c.2 off end # PCI Express Port 3
    	device pci 1c.3 off end # PCI Express Port 4
    	device pci 1c.4 off end # PCI Express Port 5
-		device pci 1c.5 on  end # PCI Express Port 6
+		device pci 1c.5 on	# PCI Express Port 6
+			register "PcieRpSlotImplemented[5]" = "1"
+		end
    	device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 on  end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1c.7 on	# PCI Express Port 8
+			register "PcieRpSlotImplemented[7]" = "1"
+		end
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
    	device pci 1d.1 off end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 on  end # PCI Express Port 13
+		device pci 1d.4 on	# PCI Express Port 13
+			register "PcieRpSlotImplemented[12]" = "1"
+		end
    	device pci 1d.5 off end # PCI Express Port 14
    	device pci 1d.6 off end # PCI Express Port 15
    	device pci 1d.7 off end # PCI Express Port 16
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2923efc..e5ceac9 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -185,6 +185,8 @@
    uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
    /* PCIe LTR(Latency Tolerance Reporting) mechanism */
    uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
+	/* Implemented as slot or built-in? */
+	uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
    /* Enable/Disable HotPlug support for Root Port */
    uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 0779ce2..51ed2a8 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -479,6 +479,8 @@

memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
           sizeof(config->PcieRpLtrEnable));
+	memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented,
+	       sizeof(config->PcieRpSlotImplemented));
    memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
           sizeof(params->PcieRpHotPlug));

Change in coreboot[master]: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )

Change subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
......................................................................

Patch Set 17:

Automatic boot test returned (PASS/FAIL/TOTAL): 6/1/7
"QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/16179
"QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/16178
"QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/16177
"QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/16176
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/16175
"HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/16181
"HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/16180

Please note: This test is under development and might not be accurate at all!