[M] Change in coreboot[master]: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M

[Jan Samek (Code Review)]

Attention is currently required from: Angel Pons, Werner Zeh.

Jan Samek has uploaded a new patch set (#3) to the change originally created by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/68223 )

Change subject: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
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mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M

Apollo Lake seems to start with PCIe root ports unusable/uninitialized
before FspMemoryInit() is called and FSP-M properly initializes these
root ports.

However, we need the root ports accessible before FspMemoryInit() in
certain cases (like this one - emitting POST codes through a PCIe
device).

For the inicialization to happen properly, certain register writes
specified in Apollo Lake IAFW vol. 2 (#559811), chapter 3.3.1, have
to be done.

BUG=none
TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check
that the POST codes are emitted before FspMemoryInit().

Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e
Signed-off-by: Angel Pons 
Signed-off-by: Jan Samek 
---
M src/mainboard/siemens/mc_apl1/bootblock.c
1 file changed, 50 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/68223/3