Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43883 )
Change subject: mb/google/glados: Relocate devicetree FSP settings ......................................................................
mb/google/glados: Relocate devicetree FSP settings
Also drop some redundant comments about these settings.
Tested with BUILD_TIMELESS=1, Caroline does not change.
Change-Id: I459c019aa99e04948ace45c589c3398768801dbe Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/glados/devicetree.cb 1 file changed, 41 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43883/1
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 84e9693..b7c0510 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -38,25 +38,12 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s @@ -64,13 +51,6 @@ register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1"
- # Enable Root port 1 - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -86,9 +66,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }"
- # I2C4 is 1.8V - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" - # PL2 override 25W register "power_limits_config" = "{ .tdp_pl2_override = 25, @@ -108,6 +85,10 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + + # FIXME: corresponding device entry is missing + register "Device4Enable" = "1" + device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem @@ -115,21 +96,35 @@ device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + + # FIXME: does not match devicetree! + register "HeciEnabled" = "0" + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA + device pci 17.0 off # SATA + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + end device pci 19.0 on end # UART #2 device pci 19.1 off end # I2C #5 - device pci 19.2 on end # I2C #4 - device pci 1c.0 on + device pci 19.2 on # I2C #4 + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + end + device pci 1c.0 on # PCI Express Port 1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" chip drivers/intel/wifi register "wake" = "GPE0_DW0_16" device pci 00.0 on end end - end # PCI Express Port 1 + end device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 @@ -145,9 +140,14 @@ device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC + device pci 1e.4 on # eMMC + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + end device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard + device pci 1e.6 off # SDCard + register "ScsSdCardEnabled" = "0" + end device pci 1f.0 on chip drivers/pc80/tpm device pnp 0c31.0 on end @@ -158,9 +158,17 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.3 on # Intel HDA + register "EnableAzalia" = "1" + end + device pci 1f.4 on # SMBus + register "SmbusEnable" = "1" + end device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 off # GbE + register "EnableLan" = "0" + end + + register "EnableTraceHub" = "0" end end
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43883 )
Change subject: mb/google/glados: Relocate devicetree FSP settings ......................................................................
Patch Set 1: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... File src/mainboard/google/glados/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 41: DspEnable could be moved to hd audio, too
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 43: SsicPortEnable move to usb?
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 44: Cio2Enable devtree missing
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43883 )
Change subject: mb/google/glados: Relocate devicetree FSP settings ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... File src/mainboard/google/glados/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 40: ProbelessTrace that's for tracehub, iirc. move to tracehub dev
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 46: SkipExtGfxScan move to gfx dev?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43883 )
Change subject: mb/google/glados: Relocate devicetree FSP settings ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... File src/mainboard/google/glados/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 40: ProbelessTrace
that's for tracehub, iirc. […]
I'll check this option later. It doesn't directly control a device.
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 41: DspEnable
could be moved to hd audio, too
I couldn't figure out if there's a dedicated device that corresponds to this option. It depends on HDA being enabled, but also needs to be used by something on I2C
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 43: SsicPortEnable
move to usb?
Does it correspond to a specific PCI device?
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 44: Cio2Enable
devtree missing
Which PCI device does this correspond to?
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 46: SkipExtGfxScan
move to gfx dev?
It's `1` everywhere. I think I can flip the default in a separate change.
Hello build bot (Jenkins), Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43883
to look at the new patch set (#2).
Change subject: mb/google/glados: Relocate devicetree settings ......................................................................
mb/google/glados: Relocate devicetree settings
Also drop some redundant comments about these settings.
Tested with BUILD_TIMELESS=1, Caroline does not change.
Change-Id: I459c019aa99e04948ace45c589c3398768801dbe Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/glados/devicetree.cb 1 file changed, 41 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43883/2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43883 )
Change subject: mb/google/glados: Relocate devicetree settings ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... File src/mainboard/google/glados/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 41: DspEnable
I couldn't figure out if there's a dedicated device that corresponds to this option. […]
well, there is no dedicated device, but it's part of hda, so why not move it there? "something on I2C" is an AFAIU optional audio codec
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 43: SsicPortEnable
Does it correspond to a specific PCI device?
it's not its own device but part of xhci
https://review.coreboot.org/c/coreboot/+/43883/1/src/mainboard/google/glados... PS1, Line 44: Cio2Enable
Which PCI device does this correspond to?
14.3, see intel doc#334658-005 or doc#332995-003EN for example
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43883 )
Change subject: mb/google/glados: Relocate devicetree settings ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)