[S] Change in coreboot[master]: soc/intel/meteorlake: Add Meteor Lake MCH device ID

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69560 )

Change subject: soc/intel/meteorlake: Add Meteor Lake MCH device ID
......................................................................

soc/intel/meteorlake: Add Meteor Lake MCH device ID

Add Meteor Lake MCH device ID 0x7d15.

TEST=Build and verify boot on MTL RVP

With patch, coreboot log:
`[DEBUG]  MCH: device id 7d15 (rev 00) is Meteorlake P`

Signed-off-by: Sridhar Siricilla 
Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/meteorlake/bootblock/report_platform.c
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/systemagent.c
5 files changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/69560/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 949afbd..68e2834 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4130,6 +4130,7 @@
 #define PCI_DID_INTEL_MTL_P_ID_1		0x7D01
 #define PCI_DID_INTEL_MTL_P_ID_2		0x7D02
 #define PCI_DID_INTEL_MTL_P_ID_3		0x7d14
+#define PCI_DID_INTEL_MTL_P_ID_4		0x7d15
 #define PCI_DID_INTEL_RPL_P_ID_1		0xa706
 #define PCI_DID_INTEL_RPL_P_ID_2		0xa707
 #define PCI_DID_INTEL_RPL_P_ID_3		0xa708
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index e74c118..90b3335 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -340,6 +340,7 @@
    PCI_DID_INTEL_MTL_P_ID_1,
    PCI_DID_INTEL_MTL_P_ID_2,
    PCI_DID_INTEL_MTL_P_ID_3,
+	PCI_DID_INTEL_MTL_P_ID_4,
    PCI_DID_INTEL_GLK_NB,
    PCI_DID_INTEL_APL_NB,
    PCI_DID_INTEL_CNL_ID_U,
diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c
index 63f1771..be7b602 100644
--- a/src/soc/intel/meteorlake/bootblock/report_platform.c
+++ b/src/soc/intel/meteorlake/bootblock/report_platform.c
@@ -28,6 +28,7 @@
    { PCI_DID_INTEL_MTL_P_ID_1, "MeteorLake P" },
    { PCI_DID_INTEL_MTL_P_ID_2, "MeteorLake P" },
    { PCI_DID_INTEL_MTL_P_ID_3, "MeteorLake P" },
+	{ PCI_DID_INTEL_MTL_P_ID_4, "MeteorLake P" },
 };

static struct {
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index b6e3ab2..19b34a2 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -22,6 +22,7 @@
    MTL_P_POWER_LIMITS_1,
    MTL_P_POWER_LIMITS_2,
    MTL_P_POWER_LIMITS_3,
+	MTL_P_POWER_LIMITS_4,
    MTL_POWER_LIMITS_COUNT
 };

diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c
index c6c1ada..c91d3bd 100644
--- a/src/soc/intel/meteorlake/systemagent.c
+++ b/src/soc/intel/meteorlake/systemagent.c
@@ -77,6 +77,9 @@
    case PCI_DID_INTEL_MTL_P_ID_3:
    	soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_3];
    	break;
+	case PCI_DID_INTEL_MTL_P_ID_4:
+		soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_4];
+		break;
    default:
    	printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipping power limits configuration\n",
    		sa_pci_id);