Change in coreboot[master]: soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slots

[Angel Pons (Code Review)]

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu.
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64036 )

Change subject: soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slots
......................................................................

soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slots

Introduce the mainboard-defined `mainboard_dimm_slot_exists()` function
to allow creating SMBIOS type 17 entries for unpopulated DIMM slots.

Change-Id: I1d9c41dd7d981842ca6f0294d9e6b0fedc0c98e4
Signed-off-by: Angel Pons 
---
M src/soc/intel/xeon_sp/cpx/ddr.c
M src/soc/intel/xeon_sp/cpx/include/soc/ddr.h
M src/soc/intel/xeon_sp/cpx/romstage.c
3 files changed, 19 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/64036/1

diff --git a/src/soc/intel/xeon_sp/cpx/ddr.c b/src/soc/intel/xeon_sp/cpx/ddr.c
index 0fa36ab..990711f 100644
--- a/src/soc/intel/xeon_sp/cpx/ddr.c
+++ b/src/soc/intel/xeon_sp/cpx/ddr.c
@@ -82,3 +82,8 @@
    else
    	return 800;
 }
+
+__weak bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot)
+{
+	return false;
+}
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h b/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h
index 61a5ebe..0ef6ded 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h
@@ -3,7 +3,7 @@
 #ifndef _CPX_DDR_H_
 #define _CPX_DDR_H_

-#include <stdint.h>
+#include <types.h>

/* DDR_*_TCK_MIN are in picoseconds */
 #define DDR_800_TCK_MIN                 2500
@@ -48,4 +48,6 @@
 uint16_t get_max_memory_speed(uint32_t commonTck);
 uint32_t get_ddr_voltage(uint8_t DdrVoltage);

+bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot);
+
 #endif /* _CPX_DDR_H_ */
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index ad794c3..4fd1c36 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -133,6 +133,17 @@
    				src_dimm.VendorID,
    				src_dimm.actKeyByte2);
    			index++;
+			} else if (mainboard_dimm_slot_exists(0, ch, dimm)) {
+				if (index >= dimm_max) {
+					printk(BIOS_WARNING, "Too many DIMMs info for %s.\n",
+						__func__);
+					return;
+				}
+				dest_dimm = &mem_info->dimm[index];
+				dest_dimm->dimm_size = 0;
+				dest_dimm->channel_num = ch;
+				dest_dimm->dimm_num = dimm;
+				index++;
    		}
    	}
    }