Change in coreboot[master]: src/soc/rockchip/rk3399/clock: Add rkclk_ddr_reset() function

[Moritz Fischer (Code Review)]

Attention is currently required from: Julius Werner.
Moritz Fischer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50889 )

Change subject: src/soc/rockchip/rk3399/clock: Add rkclk_ddr_reset() function
......................................................................

src/soc/rockchip/rk3399/clock: Add rkclk_ddr_reset() function

This adds the rkclk_ddr_reset() function equivalent for the RK3399.

Signed-off-by: Moritz Fischer 
Change-Id: If1da85064d75bdf49b7555d09257409443c25e8a
---
M src/soc/rockchip/rk3399/clock.c
1 file changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/50889/1

diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 0ba07d6..074576d 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -650,6 +650,18 @@
    	rkclk_set_dpllssc(&dpll_cfg);
 }

+#define CRU_SFTRST_DDR_CTRL(ch, n)	((0x1 << (8 + 16 + (ch) * 4)) | \
+					((n) << (8 + (ch) * 4)))
+#define CRU_SFTRST_DDR_PHY(ch, n)	((0x1 << (9 + 16 + (ch) * 4)) | \
+					((n) << (9 + (ch) * 4)))
+
+void rkclk_ddr_reset(u32 channel, u32 ctl, u32 phy)
+{
+	write32(&cru_ptr->softrst_con[4],
+		CRU_SFTRST_DDR_CTRL(channel, ctl) |
+		CRU_SFTRST_DDR_PHY(channel, phy));
+}
+
 #define SPI_CLK_REG_VALUE(bus, clk_div) \
    	RK_CLRSETBITS(CLK_SPI_PLL_SEL_MASK << \
    				CLK_SPI ##bus## _PLL_SEL_SHIFT | \