Hello Jes Klinke,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44626
to review the following change.
Change subject: soc/intel/tigerlake: Enable long cr50 ready pulses ......................................................................
soc/intel/tigerlake: Enable long cr50 ready pulses
A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code running in verstage, which will program a new Cr50 register, to have Cr50 generate longer than default interrupt pulses. This needs to be selected on all Tiger Lake systems, since Tiger Lake (and likely future Intel SoCs) require at least 100us interrupt pulses.
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137
Change-Id: I20100d72ce426203943c1788d538bb2cd9d82e11 Signed-off-by: Jes Bodi Klinke jbk@chromium.org --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/44626/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 63998d4..8718f97 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -170,6 +170,11 @@ config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC
+# Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection +# in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses. +config TPM_CR50 + select CR50_USE_LONG_INTERRUPT_PULSES + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44626 )
Change subject: soc/intel/tigerlake: Enable long cr50 ready pulses ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44626 )
Change subject: soc/intel/tigerlake: Enable long cr50 ready pulses ......................................................................
soc/intel/tigerlake: Enable long cr50 ready pulses
A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code running in verstage, which will program a new Cr50 register, to have Cr50 generate longer than default interrupt pulses. This needs to be selected on all Tiger Lake systems, since Tiger Lake (and likely future Intel SoCs) require at least 100us interrupt pulses.
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137
Change-Id: I20100d72ce426203943c1788d538bb2cd9d82e11 Signed-off-by: Jes Bodi Klinke jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44626 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 63998d4..8718f97 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -170,6 +170,11 @@ config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC
+# Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection +# in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses. +config TPM_CR50 + select CR50_USE_LONG_INTERRUPT_PULSES + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY
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Furquan Shaikh (Code Review) -
Jes Klinke (Code Review)
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Patrick Georgi (Code Review)