[S] Change in coreboot[main]: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier.

Hello Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/83495?usp=email

to look at the new patch set (#3).

Change subject: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
......................................................................

soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS

In AMD platforms, the bit 4 of CMOS's Register A (0x0a) is DV0 bank
selection (0 for Bank 0; 1 for Bank 1) [1]. Since the MC146818 driver
accesses VBNV via Bank 0, the bit must be cleared before we can save
VBNV to CMOS in verstage.

Usually there's no problem with that, because the Register A is
configured in cmos_init() in ramstage. However, if CMOS has lost power,
then in the first boot after that, the bit may contain arbitrary data in
verstage. If that bit happens to be 1, then CMOS writes in verstage will
fail.

To fix the problem, define vbnv_platform_init_cmos() to configure the
Register A (RTC_FREQ_SELECT). Static assertions are also added to make
sure the whole VBNV is accessible via Bank 0 and that the written byte
doesn't contain RTC_AMD_BANK_SELECT (bit 4). Note that the kernel driver
also ensures RTC_AMD_BANK_SELECT isn't set for AMD [2].

[1] 48751_16h_bkdg.pdf
[2] lore.kernel.org/lkml/[e-mail]

BUG=b:346716300
TEST=CMOS writes succeeded in verstage after battery cutoff
BRANCH=skyrim

Change-Id: Idf167387b403be1977ebc08daa1f40646dd8c83f
Signed-off-by: Yu-Ping Wu 
---
M src/include/pc80/mc146818rtc.h
M src/soc/amd/common/vboot/vbnv_cmos.c
2 files changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/83495/3