Change in coreboot[master]: soc/intel/alderlake: add GPIO definitions for PCH-S

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Michał Żygowski, Michał Kopeć.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63467 )

Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S
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Patch Set 1: Code-Review+1

(1 comment)

File src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h:

https://review.coreboot.org/c/coreboot/+/63467/comment/ad1a3f2b_ae8a0fe3 
PS1, Line 288: #define GPP_F20_IRQ	0x70
             : #define GPP_F21_IRQ	0x71
             : #define GPP_F22_IRQ	0x72
             : #define GPP_F23_IRQ	0x73
             : 
             : /* Group D */
             : #define GPP_D0_IRQ	0x70
             : #define GPP_D1_IRQ	0x71
             : #define GPP_D2_IRQ	0x72
             : #define GPP_D3_IRQ	0x73
is this really the way they overlap, seems odd, would expect it to start over from 0x18 like D8 does...