Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9223
-gerrit
commit 552b3dbce257d28d66ad0565797f5c0f5398713d Author: Kenji Chen kenji.chen@intel.com Date: Fri Oct 10 03:08:15 2014 +0800
Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.
Signed-off-by: Stefan Reinauer reinauer@chromium.org Original-Commit-Id: b94c8c715febe3a04bfdf52f7b69d73ece0f6faf Original-BUG=chrome-os-partner:31424 Original-TEST=Build an image and confirm the settings are correctly applied Original-to registers for PCIe L1 Sub-State feature enabling. Original-Signed-off-by: Kenji Chen kenji.chen@intel.com Original-Change-Id: I07ce6eea648b1b37d606f5529edad184e3de70ac Original-Reviewed-on: https://chromium-review.googlesource.com/222599 Original-Reviewed-by: Duncan Laurie dlaurie@chromium.org
Change-Id: I07336599797c09bf23e5b15059d6ad812fdc7c61 --- src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/broadwell/pcie.c | 7 +++++++ 2 files changed, 8 insertions(+)
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index c147663..2e70f45 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE select SMM_MODULES select SMM_TSEG select SMP diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index bd1c55a..be17874 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -611,8 +611,15 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) pci_write_config32(dev, 0x94, (device << 16) | vendor); }
+static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) +{ + /* Set max snoop and non-snoop latency for Broadwell */ + pci_mmio_write_config32(dev, off, 0x10031003); +} + static struct pci_operations pcie_ops = { .set_subsystem = pcie_set_subsystem, + .set_L1_ss_latency = pcie_set_L1_ss_max_latency, };
static struct device_operations device_ops = {