Change in coreboot[master]: soc/intel/alderlake: Add get powerinfo support

[Sumeet R Pawnikar (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59190 )

Change subject: soc/intel/alderlake: Add get powerinfo support
......................................................................

soc/intel/alderlake: Add get powerinfo support

Add get powerinfo support under acpi for Alder Lake.

BUG=b:205928013
BRANCH=None
TEST=Build and test on brya system

Change-Id: I6e7ea3b34130abd1bc09e3e90d1666a929c88c5b
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/alderlake/acpi.c
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/59190/1

diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c
index ab25646..0fb989d 100644
--- a/src/soc/intel/alderlake/acpi.c
+++ b/src/soc/intel/alderlake/acpi.c
@@ -8,6 +8,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/acpi.h>
@@ -268,6 +269,7 @@
 void soc_fill_gnvs(struct global_nvs *gnvs)
 {
    config_t *config = config_of_soc();
+	int ret;

/* Enable DPTF based on mainboard configuration */
    gnvs->dpte = config->dptf_enable;
@@ -278,6 +280,9 @@

/* Fill in Above 4GB MMIO resource */
    sa_fill_gnvs(gnvs);
+
+	/* Get the powerinfo config details */
+	ret = google_chromeec_get_powerinfo_config();
 }

int soc_madt_sci_irq_polarity(int sci)