Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6607
-gerrit
commit 9b21cd47973bc402e2a6c9e4a08447e1116ea81d Author: Martin Roth martin.roth@se-eng.com Date: Mon Aug 11 12:51:38 2014 -0600
mainboard/intel/mohonpeak: code cleanup
Code cleanup requested in commit 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000"
- Change com2 to COM2 in Kconfig text - clean up includes of headers - fix whitespace
Change-Id: I828bc4781ee7de95be5546206c5d6033b75293d9 Signed-off-by: Martin Roth martin.roth@se-eng.com --- src/mainboard/intel/mohonpeak/Kconfig | 2 +- src/mainboard/intel/mohonpeak/acpi_tables.c | 5 ++--- src/mainboard/intel/mohonpeak/gpio.h | 4 ++-- src/mainboard/intel/mohonpeak/mainboard.c | 15 --------------- src/mainboard/intel/mohonpeak/romstage.c | 23 +++++++---------------- 5 files changed, 12 insertions(+), 37 deletions(-)
diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 4632c7f..edf1fb8 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -94,6 +94,6 @@ config UART_FOR_CONSOLE int default 1 help - The Mohon Peak board uses com2 (2f8) for the serial console. + The Mohon Peak board uses COM2 (2f8) for the serial console.
endif # BOARD_INTEL_MOHONPEAK diff --git a/src/mainboard/intel/mohonpeak/acpi_tables.c b/src/mainboard/intel/mohonpeak/acpi_tables.c index 52e1af7..0349075 100644 --- a/src/mainboard/intel/mohonpeak/acpi_tables.c +++ b/src/mainboard/intel/mohonpeak/acpi_tables.c @@ -30,15 +30,14 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "northbridge/intel/fsp_rangeley/northbridge.h" +#include <southbridge/intel/fsp_rangeley/nvs.h> +#include <northbridge/intel/fsp_rangeley/northbridge.h>
extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC unsigned long acpi_create_slic(unsigned long current); #endif
-#include "southbridge/intel/fsp_rangeley/nvs.h" - static global_nvs_t *gnvs_;
static void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/intel/mohonpeak/gpio.h b/src/mainboard/intel/mohonpeak/gpio.h index f1315aa..b929c68 100644 --- a/src/mainboard/intel/mohonpeak/gpio.h +++ b/src/mainboard/intel/mohonpeak/gpio.h @@ -20,7 +20,7 @@ #ifndef MOHONPEAK_GPIO_H #define MOHONPEAK_GPIO_H
-#include "southbridge/intel/fsp_rangeley/gpio.h" +#include <southbridge/intel/fsp_rangeley/gpio.h>
/* Core GPIO */ const struct soc_gpio soc_gpio_mode = { @@ -175,4 +175,4 @@ const struct soc_gpio_map gpio_map = { }, };
-#endif +#endif /* MOHONPEAK_GPIO_H */ diff --git a/src/mainboard/intel/mohonpeak/mainboard.c b/src/mainboard/intel/mohonpeak/mainboard.c index 0274e16..7559fc2 100644 --- a/src/mainboard/intel/mohonpeak/mainboard.c +++ b/src/mainboard/intel/mohonpeak/mainboard.c @@ -18,22 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <types.h> -#include <string.h> #include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#if CONFIG_VGA_ROM_RUN -#include <x86emu/x86emu.h> -#endif -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/fsp_rangeley/soc.h>
/* * mainboard_enable is executed as first thing after enumerate_buses(). diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c index 73e5467..b1fb995 100644 --- a/src/mainboard/intel/mohonpeak/romstage.c +++ b/src/mainboard/intel/mohonpeak/romstage.c @@ -19,36 +19,27 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <stdint.h> -#include <string.h> -#include <lib.h> -#include <timestamp.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <cbmem.h> -#include <console/console.h> #include <drivers/intel/fsp/fsp_util.h> -#include <northbridge/intel/fsp_rangeley/northbridge.h> #include <southbridge/intel/fsp_rangeley/soc.h> #include <southbridge/intel/fsp_rangeley/gpio.h> #include <southbridge/intel/fsp_rangeley/romstage.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include "gpio.h"
static void interrupt_routing_config(void) { - u32 ilb_base = pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf; + u32 ilb_base = pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf;
- /* - * Initialize Interrupt Routings for each device in ilb_base_address. - * IR01 map to PCIe device 0x01 ... IR31 to device 0x1F. - * PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23. - * This should match devicetree and the ACPI IRQ routing/ - */ + /* + * Initialize Interrupt Routings for each device in ilb_base_address. + * IR01 map to PCIe device 0x01 ... IR31 to device 0x1F. + * PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23. + * This should match devicetree and the ACPI IRQ routing/ + */ write32(ilb_base + ILB_ACTL, 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */ write16(ilb_base + ILB_IR01, 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */ write16(ilb_base + ILB_IR02, 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */
-
Martin Roth