New patch to review for coreboot: smaug: Increase drive strength for QSPI Pinmux

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10945

-gerrit

commit bb259358dc034e241d0b83cd294d2c4a82229acd
Author: Furquan Shaikh 
Date:   Mon Jul 13 09:46:56 2015 -0700

smaug: Increase drive strength for QSPI Pinmux

Change the drive strength for QSPI Pinmux to DRIVE_STRENGTH_2 as per
    recommendations from nVidia hardware engineers.

BUG=chrome-os-partner:41877
    BRANCH=None
    TEST=Compiles successfully and boots to kernel prompt

Change-Id: I5a7b94acb57bbc21d277a49fd0a6b892638fc0ca
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: 58d085e6acbcd0fd355b1c7efc10606312caf8e8
    Original-Change-Id: I03dd288d2e335d40c83feaec7efbf10a7d3bf1e6
    Original-Signed-off-by: Furquan Shaikh 
    Original-Reviewed-on: https://chromium-review.googlesource.com/284959
    Original-Tested-by: Furquan Shaikh 
    Original-Reviewed-by: Aaron Durbin 
    Original-Commit-Queue: Furquan Shaikh 
    Original-Trybot-Ready: Furquan Shaikh 
---
 src/mainboard/google/smaug/bootblock.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/smaug/bootblock.c b/src/mainboard/google/smaug/bootblock.c
index ee535c2..77c8441 100644
--- a/src/mainboard/google/smaug/bootblock.c
+++ b/src/mainboard/google/smaug/bootblock.c
@@ -42,12 +42,16 @@ static const struct pad_config pmic_pads[] = {
 /********************** SPI Flash *****************************/
 static const struct pad_config spiflash_pads[] = {
    /* QSPI fLash: mosi, miso, clk, cs0, hold, wp  */
-	PAD_CFG_SFIO(QSPI_IO0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
-	PAD_CFG_SFIO(QSPI_IO1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
-	PAD_CFG_SFIO(QSPI_SCK, PINMUX_INPUT_ENABLE, QSPI),
-	PAD_CFG_SFIO(QSPI_CS_N, PINMUX_INPUT_ENABLE, QSPI),
-	PAD_CFG_SFIO(QSPI_IO2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
-	PAD_CFG_SFIO(QSPI_IO3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
+	PAD_CFG_SFIO(QSPI_IO0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP |
+		     PINMUX_DRIVE_2X, QSPI),
+	PAD_CFG_SFIO(QSPI_IO1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP |
+		     PINMUX_DRIVE_2X, QSPI),
+	PAD_CFG_SFIO(QSPI_SCK, PINMUX_INPUT_ENABLE | PINMUX_DRIVE_2X, QSPI),
+	PAD_CFG_SFIO(QSPI_CS_N, PINMUX_INPUT_ENABLE | PINMUX_DRIVE_2X, QSPI),
+	PAD_CFG_SFIO(QSPI_IO2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP |
+		     PINMUX_DRIVE_2X, QSPI),
+	PAD_CFG_SFIO(QSPI_IO3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP |
+		     PINMUX_DRIVE_2X, QSPI),
 };

/********************* TPM ************************************/