Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63472 )
Change subject: soc/intel: Remove dmi driver ......................................................................
soc/intel: Remove dmi driver
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7 --- M src/mainboard/ocp/deltalake/bootblock.c M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/cannonlake/bootblock/pch.c D src/soc/intel/common/block/dmi/Kconfig D src/soc/intel/common/block/dmi/Makefile.inc D src/soc/intel/common/block/dmi/dmi.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/pch/Kconfig M src/soc/intel/elkhartlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/xeon_sp/pch.c 14 files changed, 4 insertions(+), 139 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/63472/1
diff --git a/src/mainboard/ocp/deltalake/bootblock.c b/src/mainboard/ocp/deltalake/bootblock.c index 402b572..020c624 100644 --- a/src/mainboard/ocp/deltalake/bootblock.c +++ b/src/mainboard/ocp/deltalake/bootblock.c @@ -12,6 +12,8 @@ #include <superio/aspeed/common/aspeed.h> #include <cpxsp_dl_gpio.h>
+#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 #define ASPEED_SIO_PORT 0x2E
static void enable_espi_lpc_io_windows(void) diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 60f3a85..c27faaf 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -9,7 +9,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -39,11 +38,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - static void soc_config_pwrmbase(void) { /* diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index a4f47c9..7651cdf 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -4,7 +4,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> @@ -34,11 +33,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - static uint32_t get_pmc_reg_base(void) { if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) diff --git a/src/soc/intel/common/block/dmi/Kconfig b/src/soc/intel/common/block/dmi/Kconfig deleted file mode 100644 index 2cc4646..0000000 --- a/src/soc/intel/common/block/dmi/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -config SOC_INTEL_COMMON_BLOCK_DMI - bool - select SOC_INTEL_COMMON_BLOCK_PCR - help - Intel Processor common DMI support diff --git a/src/soc/intel/common/block/dmi/Makefile.inc b/src/soc/intel/common/block/dmi/Makefile.inc deleted file mode 100644 index 7d013c9..0000000 --- a/src/soc/intel/common/block/dmi/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y) - -bootblock-y += dmi.c -romstage-y += dmi.c -ramstage-y += dmi.c - -endif diff --git a/src/soc/intel/common/block/dmi/dmi.c b/src/soc/intel/common/block/dmi/dmi.c deleted file mode 100644 index 1a3a602..0000000 --- a/src/soc/intel/common/block/dmi/dmi.c +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <intelblocks/dmi.h> -#include <intelblocks/pcr.h> -#include <soc/pcr_ids.h> - -#define MAX_GPMR_REGS 3 - -#define GPMR_OFFSET(x) (0x277c + (x) * 8) -#define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 -#define DMI_PCR_GPMR_BASE_SHIFT 16 -#define DMI_PCR_GPMR_BASE_MASK 0xffff - -#define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) -#define DMI_PCR_GPMR_EN BIT(31) - -/* GPMR Register read given offset */ -static uint32_t gpmr_read32(uint16_t offset) -{ - return pcr_read32(PID_DMI, offset); -} - -/* GPMR Register write given offset and val */ -static void gpmr_write32(uint16_t offset, uint32_t val) -{ - return pcr_write32(PID_DMI, offset, val); -} - -/* Check for available free gpmr */ -static int get_available_gpmr(void) -{ - int i; - uint32_t val; - - for (i = 0; i < MAX_GPMR_REGS; i++) { - val = gpmr_read32(GPMR_DID_OFFSET(i)); - if (!(val & DMI_PCR_GPMR_EN)) - return i; - } - printk(BIOS_ERR, "%s: No available free gpmr found\n", __func__); - return CB_ERR; -} - -/* Configure GPMR for the given base and size of extended BIOS Region */ -enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id) -{ - int gpmr_num; - uint32_t limit; - - if (base & ~(DMI_PCR_GPMR_BASE_MASK << DMI_PCR_GPMR_BASE_SHIFT)) { - printk(BIOS_ERR, "base is not 64-KiB aligned!\n"); - return CB_ERR; - } - - limit = base + (size - 1); - - if (limit < base) { - printk(BIOS_ERR, "Invalid limit: limit cannot be less than base!\n"); - return CB_ERR; - } - - if ((limit & ~DMI_PCR_GPMR_LIMIT_MASK) != 0xffff) { - printk(BIOS_ERR, "limit does not end on a 64-KiB boundary!\n"); - return CB_ERR; - } - - /* Get available free GPMR */ - gpmr_num = get_available_gpmr(); - if (gpmr_num == CB_ERR) - return CB_ERR; - - /* Program Range for the given decode window */ - gpmr_write32(GPMR_OFFSET(gpmr_num), (limit & DMI_PCR_GPMR_LIMIT_MASK) | - ((base >> DMI_PCR_GPMR_BASE_SHIFT) & DMI_PCR_GPMR_BASE_MASK)); - - /* Program source decode enable bit and the Destination ID */ - gpmr_write32(GPMR_DID_OFFSET(gpmr_num), dest_id | DMI_PCR_GPMR_EN); - - return CB_SUCCESS; -} diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 43a3001..3590852 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -25,13 +25,6 @@ #define LPC_IOE_COMA_EN (1 << 0) #define LPC_NUM_GENERIC_IO_RANGES 4
-#define PCR_DMI_LPCLGIR1 0x2730 - -#define PCR_DMI_LPCGMR 0x2740 - -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 - /* LPC PCR configuration */ #define PCR_LPC_PRC 0x341c #define PCR_LPC_CCE_EN 0xf diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 7951298..56471c3 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -26,7 +26,6 @@ def_bool y select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CSE - select SOC_INTEL_COMMON_BLOCK_DMI select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c index 09b78be..306908f 100644 --- a/src/soc/intel/elkhartlake/bootblock/pch.c +++ b/src/soc/intel/elkhartlake/bootblock/pch.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -32,11 +31,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - static void soc_config_pwrmbase(void) { /* diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 7694a10..7ab7ed9a 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -28,11 +27,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - static void soc_config_pwrmbase(void) { /* diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index a3c338e..4de63f2 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -5,7 +5,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -32,11 +31,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - static void soc_config_pwrmbase(void) { /* diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index ec60cab..cc2d384 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -2,7 +2,6 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/itss.h> diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 7351492..9758dba 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -11,7 +11,6 @@ #include <device/device.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -42,11 +41,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - static void soc_config_pwrmbase(void) { /* diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index d2496b1..f55e7da 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -3,7 +3,6 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -#include <intelblocks/dmi.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> #include <intelblocks/p2sb.h> @@ -12,6 +11,8 @@ #include <soc/pmc.h> #include <console/console.h>
+#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC
-
Wonkyu Kim (Code Review)