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Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74296 )
Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74296/comment/43e73760_e59018b6
PS2, Line 12: By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms,
Please add a blank line between paragraphs.
Done
https://review.coreboot.org/c/coreboot/+/74296/comment/92eea8bd_20a3c007
PS2, Line 13: small total memory issue
Please elaborate.
Done
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/74296/comment/93447fc3_bb5e3c9c
PS2, Line 260: ram_from_to
use upper_ram_end()?
Done
https://review.coreboot.org/c/coreboot/+/74296/comment/f208c7eb_a3c977ae
PS2, Line 261: gi_mem_size
why is gi_mem_size subtracted in the !CONFIG(OCP_VPD) case? […]
gi_mem_size will be 0 if there's no CXL memory and it's subtracted no matter CONFIG(OCP_VPD) is selected or not. If there's no CXL memory, pds.pds[i].pd_type is always equals to PD_TYPE_PROCESSOR and will be skipped without executing fixed_mem_range_flags() below, the fixed_mem_range_flags() is only for CXL memory.
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