Change in coreboot[master]: soc/amd/common/psp_verstage: Write postcodes after ESPI init

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Jon Murphy, Rob Barnes, Fred Reitberger, Felix Held.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62880 )

Change subject: soc/amd/common/psp_verstage: Write postcodes after ESPI init
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Patch Set 1:

(1 comment)

File src/soc/amd/cezanne/Kconfig:

https://review.coreboot.org/c/coreboot/+/62880/comment/d85d0859_41a91488 
PS1, Line 348: PSP_POSTCODES_ON_ESPI
Mohan/Avinash,

Does PSP use ESPI to write postcodes by default? Also does Cezanne use Soft Fuse Bit 15 if this config is enabled?