[XS] Change in coreboot[main]: libpayload: Unconditionally handle CBMEM_ID_CSE_ entries*

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83436?usp=email )

Change subject: libpayload: Unconditionally handle CBMEM_ID_CSE_ entries*
......................................................................

libpayload: Unconditionally handle CBMEM_ID_CSE_ entries*

This change removes the unnecessary conditional compilation around
CBMEM_ID_CSE_BP_INFO and CBMEM_ID_CSE_INFO handling in
cb_parse_cbmem_entry. These CBMEM IDs are only relevant on platforms
with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD enabled, and platforms without
this config option won't encounter these IDs when calling
cb_parse_cbmem_entry().

BUG=b:305898363
TEST=Builds and boots successfully:
    * google/rex0 with SOC_INTEL_CSE_LITE_SKU
    * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD

Change-Id: Icf056f8426015e99509be5f5a67cb66468645cd9
Signed-off-by: Subrata Banik 
---
M payloads/libpayload/libc/coreboot.c
1 file changed, 0 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/83436/1

diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 1d914c5..7873426 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -262,14 +262,12 @@
    case CBMEM_ID_MEM_CHIP_INFO:
    	info->mem_chip_base = cbmem_entry->address;
    	break;
-#if CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)
    case CBMEM_ID_CSE_BP_INFO:
    	info->cse_bp_info = cbmem_entry->address;
    	break;
    case CBMEM_ID_CSE_INFO:
    	info->cse_info = cbmem_entry->address;
    	break;
-#endif
    default:
    	break;
    }