Change in coreboot[master]: mb/google/brya/var/taeko: Fix PCIE gen 4 cannot enter S0ix issue

[Joey Peng (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59176 )

Change subject: mb/google/brya/var/taeko: Fix PCIE gen 4 cannot enter S0ix issue
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mb/google/brya/var/taeko: Fix PCIE gen 4 cannot enter S0ix issue

Fix PCIE gen 4 cannot enter S0ix issue

BUG=b:205920263
TEST=emerge-brya coreboot and verify that DUT can enter S0ix 15 times

Signed-off-by: Joey Peng 
Change-Id: I8b6cbdfe4cff8360317089edc2d0f94873355d78
---
M src/mainboard/google/brya/variants/taeko/overridetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59176/1

diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index d6d7c9b..7a797dc 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -222,6 +222,12 @@
    		end
    	end
    	device ref pcie4_0 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
    		# Enable CPU PCIE RP 1 using CLK 0
    		register "cpu_pcie_rp[CPU_RP(1)]" = "{
    			.clk_req = 0,