[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

[Saurabh Mishra (Code Review)]

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
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Patch Set 62:

(1 comment)

File src/soc/intel/pantherlake/cpu.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/e37a13a2_46ffdcbf?usp... :
PS50, Line 143: disable_three_strike_error
> > Can you CC me in bug b/314883362 […]

Thank you, i have gone through the bug, corrected in MTL EDS. "Ideally 3-strike disable bit 11 should never have been placed in MSR 0x1A4 which is used for disabling prefetchers." is correct.
In PTL EDS, we see the 1ab bit 0 as (DISABLE_​SIGNALING_​THREE_​STRIKE_​EVENT) which prevents the signaling of the three-strike event once the counter has expired.

The function, "disable_signaling_three_strike_event" should be the corrected one to be used.
I am currently validating the read MSR status using iotools of 0x1ab, while using "disable_signaling_three_strike_event"
I will update soon on this.