Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68469 )
Change subject: soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles ......................................................................
soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles
Expand extra 5 DPTC thermal related profiles for Dynamic Thermal Table Switching support.
BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng ericky_cheng@compal.corp-partner.google.com Change-Id: Ie03de155325cbb340fce09848327ff7fa33ab1fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68469 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Van Patten timvp@google.com --- M src/soc/amd/mendocino/chip.h 1 file changed, 76 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Van Patten: Looks good to me, approved
diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 04241ec..11121c5 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -74,6 +74,62 @@ uint32_t vrm_maximum_current_limit_throttle_mA; uint32_t vrm_soc_current_limit_throttle_mA;
+ /* Thermal profile B*/ + uint32_t fast_ppt_limit_mW_B; + uint32_t slow_ppt_limit_mW_B; + uint32_t slow_ppt_time_constant_s_B; + uint32_t sustained_power_limit_mW_B; + uint16_t stt_min_limit_B; + uint16_t stt_m1_B; + uint16_t stt_m2_B; + uint16_t stt_c_apu_B; + uint16_t stt_skin_temp_apu_B; + + /* Thermal profile C*/ + uint32_t fast_ppt_limit_mW_C; + uint32_t slow_ppt_limit_mW_C; + uint32_t slow_ppt_time_constant_s_C; + uint32_t sustained_power_limit_mW_C; + uint16_t stt_min_limit_C; + uint16_t stt_m1_C; + uint16_t stt_m2_C; + uint16_t stt_c_apu_C; + uint16_t stt_skin_temp_apu_C; + + /* Thermal profile D*/ + uint32_t fast_ppt_limit_mW_D; + uint32_t slow_ppt_limit_mW_D; + uint32_t slow_ppt_time_constant_s_D; + uint32_t sustained_power_limit_mW_D; + uint16_t stt_min_limit_D; + uint16_t stt_m1_D; + uint16_t stt_m2_D; + uint16_t stt_c_apu_D; + uint16_t stt_skin_temp_apu_D; + + /* Thermal profile E*/ + uint32_t fast_ppt_limit_mW_E; + uint32_t slow_ppt_limit_mW_E; + uint32_t slow_ppt_time_constant_s_E; + uint32_t sustained_power_limit_mW_E; + uint16_t stt_min_limit_E; + uint16_t stt_m1_E; + uint16_t stt_m2_E; + uint16_t stt_c_apu_E; + uint16_t stt_skin_temp_apu_E; + + + /* Thermal profile F*/ + uint32_t fast_ppt_limit_mW_F; + uint32_t slow_ppt_limit_mW_F; + uint32_t slow_ppt_time_constant_s_F; + uint32_t sustained_power_limit_mW_F; + uint16_t stt_min_limit_F; + uint16_t stt_m1_F; + uint16_t stt_m2_F; + uint16_t stt_c_apu_F; + uint16_t stt_skin_temp_apu_F; + uint8_t smartshift_enable;
uint8_t system_configuration;