[S] Change in coreboot[master]: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time

[Patrick Rudolph (Code Review)]

Attention is currently required from: Johnny Lin, Paul Menzel, Christian Walter, Arthur Heymans, Shuming Chu (Shuming).

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 )

Change subject: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time
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Patch Set 6: Code-Review-1

(1 comment)

Patchset:

PS6:
> > I'm not sure if this is still needed. Archer City 2S boots quite fast. […]

Boot time on our Archer City 2S is about 2 minutes.

**Without this commit:**
Timestamp - calling FspSiliconInit: 50750376 usec
POST: 0x93
FSPS returned 0
Timestamp - returning from FspSiliconInit: 58548788 usec

**With this commit:**
Timestamp - calling FspSiliconInit: 51050834 usec
POST: 0x93
FSPS returned 0
Timestamp - returning from FspSiliconInit: 58782118 usec